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Showing items 1-2 of 2 (1 Page(s) Totally) 1 View [10|25|50] records per page
| 亞洲大學 |
2013-10 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
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Ankit Kumar;Emita Yulia;Emita Yulia Hapsari;Vasanth Kuma;Vasanth Kumar;Aryadeep Mri;Aryadeep Mrinal;許健;Gene Sheu;楊紹明;Shao-Ming Yang;Vivek Ningar |
| 亞洲大學 |
2013-10 |
Optimization of SiC Schottky Diode using Linear P for Edge Termination
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Mri, Aryadeep;Aryadeep Mrinal, ;Kumar, Vijay;Vijay Kumar M P, ;Vivek N, ;Vivek N, ;Manjunatha, M;Manjunatha M, ;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
Showing items 1-2 of 2 (1 Page(s) Totally) 1 View [10|25|50] records per page
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