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Showing items 1-5 of 5 (1 Page(s) Totally)
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| 國立交通大學 |
2018-08-21T05:56:55Z |
Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step
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Chang, Chia-Ling (Lynn); Wen, Charles H. -P; Bhadra, Jayanta |
| 國立交通大學 |
2017-04-21T06:49:33Z |
Portable simulation/emulation stimulus on an industrial-strength SoC
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Torres, Francisco; Srivastava, Rohit; Ruiz, Javier; Wen, H. -P.; Bose, Mrinal; Bhadra, Jayanta |
| 國立交通大學 |
2014-12-08T15:24:33Z |
An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
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Chang, Chia-Ling (Lynn); Chang, Chia-Ching (Austin); Chan, Hui-Ling; Wen, Charles H. -P.; Bhadra, Jayanta |
| 國立交通大學 |
2014-12-08T15:19:58Z |
Speeding up Bounded Sequential Equivalence Checking with Cross-Timeframe State-Pair Constraints from Data Learning
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Chang, Chia-Ling(Lynn); Wen, Charles H. -P.; Bhadra, Jayanta |
| 國立交通大學 |
2014-12-08T15:12:33Z |
An incremental learning framework for estimating signal controllability in unit-level verification
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Wen, Charles H. -P.; Wang, Li-C.; Bhadra, Jayanta |
Showing items 1-5 of 5 (1 Page(s) Totally)
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