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Showing items 31-40 of 69 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:27:59Z |
ANALYZING CACHE PERFORMANCE ON MULTI-STREAM EXECUTION PROCESSOR
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LIN, CZ; TSENG, CC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:27:37Z |
Register renaming for x86 superscalar design
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Liu, CC; Shiu, RM; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:30Z |
Instruction cache prefetching with extended BTB
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Chi, SA; Shiu, RM; Chiu, JC; Chang, SE; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:25Z |
Instruction folding in Java processor
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Ton, LR; Chang, LC; Rao, MF; Tseng, HM; Shang, SS; Ma, RL; Wang, DC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:03Z |
Design of instruction stream buffer with trace support for x86 processors
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Chiu, JC; Huang, IH; Chung, CP |
| 國立交通大學 |
2014-12-08T15:26:35Z |
Code compression by register operand dependency
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Lin, K; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:26:14Z |
A statistics-based approach to incrementally update inverted files
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Shieh, WY; Chung, CP |
| 國立交通大學 |
2014-12-08T15:26:14Z |
A tree-based inverted file for fast ranked-document retrieval
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Shieh, WY; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:25:51Z |
A unique-order interpolative code for fast querying and space-efficient indexing in information retrieval systems
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Cheng, CS; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:25:38Z |
Low-power BIBITS encoding with register relabeling for instruction bus
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Cheng, CT; Chiao, WH; Shann, JJJ; Chung, CP; Chen, WF |
Showing items 31-40 of 69 (7 Page(s) Totally)
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