臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	機構典藏計畫網站
	ROAR
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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T09:50:53Z	A wideband programmable-gain amplifier for 60GHz applications in 65nm CMOS	Y.-K. Hsieh;H.-H. Hsieh;L.-H. Lu; Y.-K. Hsieh; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T08:47:22Z	A V-Band divide-by-four direct injection-locked frequency divider in 0.18-um CMOS	H.-H. Hsieh; H.-S. Chen; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T08:19:08Z	A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL	C.-T. Lu;H.-H. Hsieh;L.-H. Lu; C.-T. Lu; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T07:43:05Z	A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS	H.-H. Hsieh;L.-H. Lu; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T07:43:05Z	A 10 GHz phase-locked loop with a compact low-pass filter in 0.18 μm CMOS	S.-J. Li;H.-H. Hsieh;L.-H. Lu; S.-J. Li; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T07:43:05Z	A 0.6 V low-power wide-range delay-locked loop in 0.18 µm CMOS	C.-T. Lu;H.-H. Hsieh;L.-H. Lu; C.-T. Lu; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T07:43:05Z	An experimental ultra-low-voltage demodulator in 0.18 µm CMOS	L.-S. Lai;H.-H. Hsieh;P.-S. Weng;L.-H. Lu; L.-S. Lai; H.-H. Hsieh; P.-S. Weng; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T07:09:30Z	Gain-enhancement techniques for CMOS folded cascode LNAs at low-voltage operations	H.-H. Hsieh; J.-H. Wang; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T07:09:30Z	An image-band-rejection technique for error detection of on-chip quadrature phases	L.-S. Lai; H.-H. Hsieh; L.-H. Lu; L.-S. Lai; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2018-09-10T07:09:29Z	A 24-GHz receiver frontend with a LO signal generator in 0.18-um CMOS	Y.-H. Chen;H.-H. Hsieh;L.-H. Lu; Y.-H. Chen; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU

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