臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
元智大學	2015-03-16	Granularity of Via Configurable Logic Block for Structured ASIC	Hui-Hsiang Tung; Lin R.-B.
元智大學	2012-12	Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow	Hui-Hsiang Tung; Lin R.-B.; Mei-Chen Li; Tsung-Han Heish
元智大學	2012	降低光罩成本之類標準元件穿孔可程式的結構化客製晶片	董慧香; Hui-Hsiang Tung
元智大學	2010-12	Via-configurable Logic Block Architectures for Standard Cell like Structured ASICs	林榮彬; Hui-Hsiang Tung; Yu-Chen Chen; Da-Wei Hsu; Shih-Jung Hsu; Sin-Yu Chen
元智大學	2010-05	Via Configurable Three-Input Lookup-Tables for Structured ASICs	林榮彬; Yu-Chen Chen; Hou-Yu Pang; Kuen-Wen Lin; Hui-Hsiang Tung; Shih-Chieh Su
元智大學	2010-03	Power Gating Design for Standard-Cell-Like Structured ASICs	林榮彬; Sin-Yu Chen; Hui-Hsiang Tung; Kuen-Wey Lin
元智大學	2009-12	Using Structured ASIC to Improve Design Productivity	林榮彬; Yu-Wen Tsai; Kun-Chen Wu; Hui-Hsiang Tung
元智大學	2008-04	Standard cell like via-configurable logic block for structured ASICs	林榮彬; Mei-Chen Li; Hui-Hsiang Tung; Chien-Chung Lai
元智大學	1997	不同到達時間的多元輸入訊號覆疊之元件時序特性化	董慧香; Hui-Hsiang Tung

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