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"hwang wei"的相關文件
顯示項目 26-35 / 202 (共21頁)
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| 國立交通大學 |
2017-04-21T06:49:42Z |
0.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOS
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Huang, Po-Tsang; Lai, Shu-Lin; Chuang, Ching-Te; Hwang, Wei; Huang, Jason; Hu, Angelo; Kan, Paul; Jia, Michael; Lv, Kimi; Zhang, Bright |
| 國立交通大學 |
2017-04-21T06:49:42Z |
A low-power low-swing single-ended multi-port SRAM
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Yang, Hao-, I; Chang, Ming-Hung; Lai, Ssu-Yun; Wang, Hsiang-Fei; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:16Z |
Custom 6-R, 2-or 4-W Multi-Port Register Files in an ASIC SOC with a DVFS Window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS Technology
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Hsieh, Henry; Dhong, Sang H.; Lin, Cheng-Chung; Kuo, Ming-Zhang; Tseng, Kuo-Feng; Yang, Ping-Lin; Huang, Kevin; Wang, Min-Jer; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Multiple Output Switched Capacitor DC-DC Converter with Capacitor Sharing for Sensor-Fusion Platforms
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Liang, Yu-Jie; Chen, Po-Ilung; Lu, Hung-Pin; Chu, Yuan-Hua; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:05Z |
28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
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Hsu, Wei-Shen; Huang, Po-Tsang; Wu, Shang-Lin; Chuang, Ching-Te; Hwang, Wei; Tu, Ming-Hsien; Yin, Ming-Yu |
| 國立交通大學 |
2017-04-21T06:49:03Z |
An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC Applications
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Wu, Chung-Shiang; Lin, Kai-Chun; Kuo, Yi-Ping; Chen, Po-Hung; Chu, Yuan-Hua; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:48:57Z |
Polymer TSV Fabrication Scheme with Its Electrical and Reliability Test Vehicle
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Lee, Shih-Wei; Shih, Jian-Yu; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chen, Kuan-Neng |
| 國立交通大學 |
2017-04-21T06:48:56Z |
Recent Advances in ASIC-compatible Circuit Techniques for a SOC in Newly Emerging Application Areas: Invited Paper
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Dhong, Sang H.; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:48:47Z |
A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS
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Kuo, Ming-Zhang; Hsieh, Henry; Dhong, Sang; Yang, Ping-Lin; Lin, Cheng-Chung; Tseng, Ryan; Huang, Kevin; Wang, Min-Jer; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:48:47Z |
A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOC
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Dhong, Sang; Guo, Richard; Kuo, Ming-Zhang; Yang, Ping-Lin; Lin, Cheng-Chung; Huang, Kevin; Wang, Min-Jer; Hwang, Wei |
顯示項目 26-35 / 202 (共21頁)
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