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"hwang wei"的相關文件
顯示項目 11-35 / 202 (共9頁)
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| 國立交通大學 |
2018-01-24T07:42:46Z |
應用於高效率影像壓縮之能源考量高頻寬記憶體系統
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彭世帆; 黃威; Peng, Shih-Fan; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:42:16Z |
應用於高密度神經感測之低功率神經訊號放大器
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何寬倫; 莊景德; 黃威; Ho,Kuan-Lun; Chuang,Ching-Te; Hwang,Wei |
| 國立交通大學 |
2018-01-24T07:42:16Z |
應用於物聯網之28奈米4kb 1寫2讀次臨界施密特觸發器先進先出隨機靜態存取記憶體設計
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曾煥然; 莊景德; 黃威; Tseng, Huan-Jan; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:42:11Z |
應用於卷積類神經網路之具能源效益加速器及資料處理流程
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陳致強; 黃威; Chen, Chih-Chiang; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:42:01Z |
28奈米近臨界電壓使用12顆電晶體搭配短反或閘型匹配線之管線化的三態內容可定址記憶體
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陳俊丞; 莊景德; 黃威; Chen, Jyun-Cheng; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:38:52Z |
應用於近記憶體資料處理系統之高頻寬三維堆疊動態記憶體控制單元
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林昱諠; 黃威; Lin, Yu-Hsuan; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:38:52Z |
應用於生醫感測及物聯網平台之28奈米極低功率近/次臨界多使用者先進先出記憶體設計
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吳逸群; 黃威; Wu, Yi-Chun; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:38:52Z |
應用於物聯網路由器之面積與功率效率可重複構造多重佇列架構
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林于滔; 黃威; Lin, Yu-Tao; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:38:01Z |
應用於生醫感測平台之 28 奈米極低功率近/次臨界 先進先出記憶體設計
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徐維伸; 莊景德; 黃威; Hsu, Wei-Shen; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:37:55Z |
實現在28奈米製程下0.4V近臨界電壓之三態內容可定址記憶體設計
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詹耘昇; 莊景德; 黃威; Chan, Yun-Sheng; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:56:36Z |
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement
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Wu, Chung-Shiang; Lee, Hui-Hsuan; Chen, Po-Hung; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:50:15Z |
Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable mu-Needles Array, Biocompatible Flexible Interposer, and Neural Recording Circuits
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Huang, Yu-Chieh; Hu, Yu-Chen; Huang, Po-Tsang; Wu, Shang-Lin; You, Yan-Huei; Chen, Jr-Ming; Huang, Yan-Yu; Chang, Hsiao-Chun; Lin, Yen-Han; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chuang, Ching-Te; Chiou, Jin-Chern; Chen, Kuan-Neng |
| 國立交通大學 |
2017-04-21T06:50:10Z |
Energy-Efficient Gas Recognition System with Event-Driven Power Control
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Huang, Chun-Ying; Huang, Po-Tsang; Yang, Chih-Chao; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:50:07Z |
An Ultra-High-Density 256-channel/25mm(2) Neural Sensing Microsystem using TSV-embedded Neural Probes
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Huang, Yu-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Hui, Yu-Chen; You, Yan-Huei; Chen, Jr-Ming; Huang, Yan-Yu; Chang, Hsiao-Chun; Lin, Yen-Han; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chen, Kuan-Neng; Chuang, Ching-Te; Chiou, Jin-Chern |
| 國立交通大學 |
2017-04-21T06:49:59Z |
High Efficiency Power Management System for Solar Energy Harvesting Applications
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Chang, Ming-Hung; Wu, Jung-Yi; Hsieh, Wei-Chih; Lin, Shang-Yuan; Liang, You-Wei; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:42Z |
0.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOS
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Huang, Po-Tsang; Lai, Shu-Lin; Chuang, Ching-Te; Hwang, Wei; Huang, Jason; Hu, Angelo; Kan, Paul; Jia, Michael; Lv, Kimi; Zhang, Bright |
| 國立交通大學 |
2017-04-21T06:49:42Z |
A low-power low-swing single-ended multi-port SRAM
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Yang, Hao-, I; Chang, Ming-Hung; Lai, Ssu-Yun; Wang, Hsiang-Fei; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:16Z |
Custom 6-R, 2-or 4-W Multi-Port Register Files in an ASIC SOC with a DVFS Window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS Technology
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Hsieh, Henry; Dhong, Sang H.; Lin, Cheng-Chung; Kuo, Ming-Zhang; Tseng, Kuo-Feng; Yang, Ping-Lin; Huang, Kevin; Wang, Min-Jer; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Multiple Output Switched Capacitor DC-DC Converter with Capacitor Sharing for Sensor-Fusion Platforms
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Liang, Yu-Jie; Chen, Po-Ilung; Lu, Hung-Pin; Chu, Yuan-Hua; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:49:05Z |
28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
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Hsu, Wei-Shen; Huang, Po-Tsang; Wu, Shang-Lin; Chuang, Ching-Te; Hwang, Wei; Tu, Ming-Hsien; Yin, Ming-Yu |
| 國立交通大學 |
2017-04-21T06:49:03Z |
An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC Applications
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Wu, Chung-Shiang; Lin, Kai-Chun; Kuo, Yi-Ping; Chen, Po-Hung; Chu, Yuan-Hua; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:48:57Z |
Polymer TSV Fabrication Scheme with Its Electrical and Reliability Test Vehicle
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Lee, Shih-Wei; Shih, Jian-Yu; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chen, Kuan-Neng |
| 國立交通大學 |
2017-04-21T06:48:56Z |
Recent Advances in ASIC-compatible Circuit Techniques for a SOC in Newly Emerging Application Areas: Invited Paper
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Dhong, Sang H.; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:48:47Z |
A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS
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Kuo, Ming-Zhang; Hsieh, Henry; Dhong, Sang; Yang, Ping-Lin; Lin, Cheng-Chung; Tseng, Ryan; Huang, Kevin; Wang, Min-Jer; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:48:47Z |
A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOC
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Dhong, Sang; Guo, Richard; Kuo, Ming-Zhang; Yang, Ping-Lin; Lin, Cheng-Chung; Huang, Kevin; Wang, Min-Jer; Hwang, Wei |
顯示項目 11-35 / 202 (共9頁)
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