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Showing items 126-175 of 202 (5 Page(s) Totally)
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| 國立交通大學 |
2014-12-12T01:55:18Z |
可用於低電壓動態電壓與頻率調節系統之多相時脈設計與電壓準位轉換設計
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陳美維; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:46:42Z |
實現在40奈米製程技術下可操縱在低操縱電壓的512Kb 8T靜態隨機存取記憶體
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陳建亨; Chen, Chien-Hen; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:46:42Z |
近/次臨界靜態隨機存取記憶體為基礎的先進先出記憶體設計於近身無線網路的設計和實作
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杜威宏; Du, Wei-Hung; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:46:42Z |
超低動態電壓基於頻率比之製程、電壓、溫度感測器與其應用
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林上圓; Lin, Shang-Yaun; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:46:41Z |
用於矽穿孔之三維積體電路完整電源供應之分析
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楊博任; Yang, Po-Jen; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:37:36Z |
用於矽穿孔之三維積體電路完整電源供應之分析
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林天鴻; Lin, Tien-Hung; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:37:36Z |
極低功率次/近臨界靜態隨機存取記憶體設計於動態電源調整先進先出記憶體
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邱議德; Chiu, Yi-Te; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:37:34Z |
應用於無線影像娛樂系統的隨選記憶體系統
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張雍; Chang, Yung; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:37:34Z |
可用於工作在次臨界╱近臨界電壓區間綠色節能科技之製程、電壓、溫度高適應性超低電壓時脈系統設計
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謝忠穎; Hsieh, Chung-Ying; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:36:16Z |
低功率正反器與可重置的先進先出暫存器設計
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蔡志侃; Tsai, Chi-Ken; 黃威; Hwang Wei |
| 國立交通大學 |
2014-12-12T01:27:24Z |
應用於太陽能之高效率的電源管理系統
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吳俊毅; Wu, Chun-Yi; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:27:22Z |
全數位寬電壓範圍寬頻率範圍延遲鎖定迴路時脈產生器設計
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張益銘; Chang, Yi-Ming; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:27:20Z |
低功率8T靜態隨機存取記憶體和次臨界多埠暫存器的設計與實現
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楊仕祺; Yang, Shyh-Chyi; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:27:19Z |
基於漢明差值與觸動計數模型之差分能量分析與實作-以AES晶片為例
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魏廷聿; Wei, Ting-Yu; 張錫嘉; 黃威; Chang, Hsie-Chia; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:24:38Z |
適用於高能源效率晶片之可感知變異超低電壓設計
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張銘宏; Chang, Ming-Hung; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:23:24Z |
高可靠度奈米級靜態隨機存取記憶體設計： 可靠度分析與改善技術
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楊皓義; Yang, Hao-I; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:23:20Z |
應用於無線影像娛樂系統之以記憶體為重心的晶內互聯網路
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王湘斐; Wang, Shiang-Fei; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:22:35Z |
適用於二維及矽穿孔三維積體電路之適應性功率管理設計
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謝維致; Hsieh, Wei-Chih; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:21:40Z |
應用於多核心系統晶片之節能晶內資料傳輸－以記憶儲存為重心
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黃柏蒼; Huang, Po-Tsang; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:47:26Z |
A Fully-Differential Subthreshold SRAM Cell with Auto-Compensation
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Chang, Mu-Tien; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:46:20Z |
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
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Chuang, Li-Pu; Chang, Ming-Hung; Huang, Po-Tsang; Kan, Chih-Hao; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:46:19Z |
"Green" micro-architecture and circuit co-design for ternary content addressable memory
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Huang, Po-Tsang; Chang, Shu-Wei; Liu, Wen-Yen; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:57Z |
A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibration
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Chang, Ming-Hung; Chuang, Li-Pu; Chang, I-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:56Z |
IN-SITU SELF-AWARE ADAPTIVE POWER CONTROL SYSTEM WITH MULTI-MODE POWER GATING NETWORK
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Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:55Z |
A ROBUST ULTRA-LOW POWER ASYNCHRONOUS FIFO MEMORY WITH SELF-ADAPTIVE POWER CONTROL
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Chang, Mu-Tien; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:38:51Z |
Fully On-Chip Temperature, Process, and Voltage Sensors
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Chen, Shi-Wen; Chang, Ming-Hung; Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:38:49Z |
Low Quiescent Current Variable Output Digital Controlled Voltage Regulator
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Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:37:44Z |
Impacts of gate-oxide breakdown on power-gated SRAM
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Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:37:31Z |
A 65 nm 0.165 fJ/Bit/Search 256 x 144 TCAM Macro Design for IPv6 Lookup Tables
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Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:47Z |
Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications
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Huang, Teng-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chen, Kuan-Neng; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:46Z |
Low Temperature (< 180 degrees C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration
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Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:46Z |
Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications
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Chang, Ming-Hung; Hsieh, Wei-Chih; Wu, Pei-Chen; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Ting, Chun-Yen; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:45Z |
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
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Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang |
| 國立交通大學 |
2014-12-08T15:35:44Z |
Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection
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Chang, Ming-Hung; Lin, Shang-Yuan; Wu, Pei-Chen; Zakoretska, Olesya; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:28Z |
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
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Wang, Dao-Ping; Lin, Hon-Jarn; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:19Z |
Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration
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Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:16Z |
Low Temperature (< 180 degrees C) Bonding for 3D Integration
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Huang, Yan-Pin; Tzeng, Ruoh-Ning; Chien, Yu-San; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:05Z |
A TSV-Based Bio-Signal Package With mu-Probe Array
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Chou, Lei-Chun; Lee, Shih-Wei; Huang, Po-Tsang; Chang, Chih-Wei; Chiang, Cheng-Hao; Wu, Shang-Lin; Chuang, Ching-Te; Chiou, Jin-Chern; Hwang, Wei; Wu, Chung-Hsi; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:33:26Z |
Novel Cu-to-Cu Bonding With Ti Passivation at 180 degrees C in 3-D Integration
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Huang, Yan-Pin; Chien, Yu-San; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:33:15Z |
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM
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Yang, Hao-I.; Yang, Shyh-Chyi; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:31:09Z |
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices
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Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:31:08Z |
Adaptive Power Control Technique on Power-Gated Circuitries
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Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
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Chiang, Cheng-Hao; Hu, Yu-Chen; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations
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Hu, Yu-Chen; Chiang, Cheng-Hao; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:06Z |
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
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Yang, Hao-I; Lin, Yi-Wei; Hsia, Mao-Chih; Lin, Geng-Cing; Chang, Chi-Shin; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:30:05Z |
Substrate Noise Suppression Technique for Power Integrity of TSV 3D Integration
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Yang, Po-Jen; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
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Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:40Z |
TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM
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Yang, Shyh-Chyi; Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:25Z |
A MICRO-WATT MULTI-PORT REGISTER FILE WITH WIDE OPERATING VOLTAGE RANGE
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Yang, Shyh-Chyi; Yang, Hao-I; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
Showing items 126-175 of 202 (5 Page(s) Totally)
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