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机构	日期	题名	作者
臺大學術典藏	2018-09-10T07:08:18Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application	JAMES-B KUO; B. Chung; J. B. Kuo
臺大學術典藏	2018-09-10T07:08:18Z	Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect	I. S. Lin;V. C. Su;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect	I. S. Lin;V. C. Su;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Shallow-trench-isolation (STI)-induced mechanical-stress-related kink-effect behaviors of 40-nm PD SOI NMOS device	I. S. Lin;V. C. Su;J. B. Kuo;R. Lee;G. S. Lin;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; R. Lee; G. S. Lin; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Shallow-trench-isolation (STI)-induced mechanical-stress-related kink-effect behaviors of 40-nm PD SOI NMOS device	I. S. Lin;V. C. Su;J. B. Kuo;R. Lee;G. S. Lin;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; R. Lee; G. S. Lin; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region	I. S. Lin;J. B. Kuo; I. S. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region	I. S. Lin;J. B. Kuo; I. S. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	STI-Induced Mechanical-Stress-Related Kink Effect of 40nm PD SOI NMOS Devices	I. S. Lin; V. C. Su; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Analysis of STI Mechanical-Stress Induced Effects of Nanometer PD SOI NMOS Devices	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Analysis of STI Mechanical-Stress Induced Effects of Nanometer PD SOI NMOS Devices	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	STI-Induced Mechanical Stress-Related Breakdown Behavior of 40nm PD SOI NMOS Devices	J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T06:35:01Z	Modeling the Drain Current of DG FD SOI NMOS Devices with N+/P+ Top/Bottom Gate	C. H. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T06:35:00Z	Triple Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS	H. Chen; J. B. Kuo; M. Syrzycki; JAMES-B KUO
臺大學術典藏	2018-09-10T06:35:00Z	Low-Voltage Single-Phase Clocking Adiabatic DCVS Logic Circuit with Pass Gate Logic	E. K. Loo; J. B. Kuo; M. Syrzycki; JAMES-B KUO
臺大學術典藏	2018-09-10T06:35:00Z	Modeling the Gate Tunneling Current Effects of Sub-100nm NMOS Devices with an Ultra-thin (1nm) Gate Oxide	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T06:35:00Z	STI Mechanical Stress Induced Subthreshold Kink Effect of 40nm PD SOI NMOS Devices	J. B. kuo; M. Ma; C. T. Tsai; C. S. Yeh; D. Chen; JAMES-B KUO; I. Lin; V. Su
臺大學術典藏	2018-09-10T06:34:59Z	Narrow Band Gap Semiconductor	H. H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T06:34:59Z	Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology	H. I. Chen;E. K. Loo;J. B. Kuo;M. J. Syrzycki; H. I. Chen; E. K. Loo; J. B. Kuo; M. J. Syrzycki; JAMES-B KUO
臺大學術典藏	2018-09-10T06:34:59Z	Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology	H. I. Chen;E. K. Loo;J. B. Kuo;M. J. Syrzycki; H. I. Chen; E. K. Loo; J. B. Kuo; M. J. Syrzycki; JAMES-B KUO
臺大學術典藏	2018-09-10T06:02:16Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique	B. Chung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T06:02:16Z	Analysis of Fringing Electric Field Related Capacitance Behavior of Narrow-Channel FD SOI NMOS Devices Using 3D Simulation	C. C. Chen; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO
臺大學術典藏	2018-09-10T06:02:15Z	Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide	C. H. Lin; J. B. KUO; K. W. Su; S. Liu; JAMES-B KUO
臺大學術典藏	2018-09-10T06:02:15Z	Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D simulation	Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO
臺大學術典藏	2018-09-10T06:02:15Z	Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOINMOS device considering the 3-D fringing capacitances using 3-D simulation	C. C. Chen; J. B. Kuo; K. W. Su,; S. Liu; JAMES-B KUO
臺大學術典藏	2018-09-10T06:02:15Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology	B. Chung; J. B. Kuo; JAMES-B KUO

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