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機構	日期	題名	作者
臺大學術典藏	2018-09-10T07:41:36Z	Temperature-Dependent Kink Effect Model for Partially-Depleted SOI NMOS Devices	S. C Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:36Z	Bandgap Narrowing	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:36Z	Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide	C. H. Lin;J. B. Kuo; C. H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:36Z	Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide	C. H. Lin;J. B. Kuo; C. H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:36Z	Compact MOS/Bipolar Charge-Control Model of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation---SOI-Technology (ST)-SPICE	J. B. Kuo; K. W. Su; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:36Z	A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially Depleted SOI Dynamic-Threshold Technique	S. C. Liu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:36Z	Semiconductor R&D in Taiwan	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:35Z	A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems	P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:35Z	A Low-Voltage Semi-Dynamic DCVSPG-Domino Logic Circuit	J. H. Lou; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:35Z	Modeling of Deep-Submicron SOI CMOS VLSI Devices	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications	R. Chen; R. Liu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	Analysis of STI Mechanical-Stress Induced Effects on 40nm PD SOI NMOS Devices	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	Analysis of STI Mechanical-Stress Induced Effects on 40nm PD SOI NMOS Devices	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	Transient Behavior of 40nm PD SOI NMOS Device Considering STI-Induced Mechanical Stress Effects	J. S. Su;J. B. Kuo; J. S. Su; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	Transient Behavior of 40nm PD SOI NMOS Device Considering STI-Induced Mechanical Stress Effects	J. S. Su;J. B. Kuo; J. S. Su; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	STI Mechanical-Stress Induced Small-Geometry Effect on Hysteresis Phenomenon of 40nm PD SOI NMOS Device	H. J. Hung;J. I. Lu;J. B. Kuo;G. S. Lin;C. S. Yeh;C. T. Tsai;M. Ma; H. J. Hung; J. I. Lu; J. B. Kuo; G. S. Lin; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	STI Mechanical-Stress Induced Small-Geometry Effect on Hysteresis Phenomenon of 40nm PD SOI NMOS Device	H. J. Hung;J. I. Lu;J. B. Kuo;G. S. Lin;C. S. Yeh;C. T. Tsai;M. Ma; H. J. Hung; J. I. Lu; J. B. Kuo; G. S. Lin; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	Compact Modeling of Sub-90nm CMOS VLSI Devices Considering Fringing Electric Field Effects	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	Compact Modeling of Sub-90nm CMOS VLSI Devices Considering Fringing Electric Field Effects	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:19Z	CMOS VLSI Engineering: Silicon-on-Insulator (SOI)	J. B. Kuo; K. W. Su; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application	JAMES-B KUO; B. Chung; J. B. Kuo
臺大學術典藏	2018-09-10T07:08:18Z	Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect	I. S. Lin;V. C. Su;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect	I. S. Lin;V. C. Su;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Shallow-trench-isolation (STI)-induced mechanical-stress-related kink-effect behaviors of 40-nm PD SOI NMOS device	I. S. Lin;V. C. Su;J. B. Kuo;R. Lee;G. S. Lin;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; R. Lee; G. S. Lin; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO
臺大學術典藏	2018-09-10T07:08:18Z	Shallow-trench-isolation (STI)-induced mechanical-stress-related kink-effect behaviors of 40-nm PD SOI NMOS device	I. S. Lin;V. C. Su;J. B. Kuo;R. Lee;G. S. Lin;D. Chen;C. S. Yeh;C. T. Tsai;M. Ma; I. S. Lin; V. C. Su; J. B. Kuo; R. Lee; G. S. Lin; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO

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