臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	機構典藏計畫網站
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	OpenDOAR
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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:26:16Z	Design, automation, and test for low-power and reliable flexible electronics	T.-C. Huang;J.-L. Huang;K.-T. Cheng; T.-C. Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T15:26:16Z	A Test-Application-Count Based Learning Technique for Test Time Reduction	G.-Y. Lin;K.-H. Tsai;J.-L. Huang;W.-T. Cheng; G.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T15:00:40Z	FPGA-Based Subset Sum Delay Lines	C.-Y. Wang;Y.-Y. Chen;J.-L. Huang;X.-L. Huang; C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:53Z	Fault Scrambling Techniques for Yield Enhancement of Embedded Memories	S.-K. Lu;H.-C. Jheng;M. Hashizume;J.-L. Huang;P. Ning; S.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:52Z	Synergistic reliability and yield enhancement techniques for embedded SRAMs	S.-K. Lu;H.-H. Huang;J.-L. Huang;P. Ning; S.-K. Lu; H.-H. Huang; J.-L. Huang; P. Ning; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:52Z	Improve speed path identification with suspect path expressions	J.-L. Huang;K.-H. Tsai;Y.-P. Liu;R. Guo;M. Sharma;W.-T. Cheng; J.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:52Z	A mutual characterization based SAR ADC self-testing technique	H.-J. Lin;X.-L. Huang;J.-L. Huang; H.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:52Z	A circular pipeline processing based deterministic parallel test pattern generator	K.-W. Yeh;J.-L. Huang;H.-J. Chao;L.-T. Wang; K.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:52Z	Implementation of programmable delay lines on off-the-shelf FPGAs	Y.-Y. Chen;J.-L. Huang;T. Kuo; Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:52Z	An IDDQ-Based Source Driver IC Design-for-Test Technique	S.-S. Lin;C.-L. Kao;J.-L. Huang;C.-C. Lee;X.-L. Huang; S.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:50:52Z	On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression	K. Enokimoto;X. Wen;K. Miyase;J.-L. Huang;S. Kajihara;L.-T. Wang; K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:25:31Z	Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,	S. Wu;L. T. Wang;X. Wen;W. B. Jone;M. S. Hsiao;F. Li;J. C. M. Li;J. L. Huang; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:25:29Z	An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration	X.-L. Huang;J.-L. Huang;H.-I. Chen;C.-Y. Chen;K.-T. Tseng;M.-F. Huang;Y.-F. Chou;D.-M. Kwai; X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:25:29Z	A SAR ADC missing-decision level detection and removal technique	X.-L. Huang;J.-L. Huang;Y.-F. Chou;D.-M. Kwai; X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:25:29Z	A fault-tolerant PE array based matrix multiplier design	B.-Y. Jan;J.-L. Huang; B.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:25:29Z	A transition isolation scan cell design for low shift and capture power	Y.-T. Lin;J.-L. Huang;X. Wen; Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:25:29Z	Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications	Y.-H. Chou;J.-L. Huang;X.-L. Huang; Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:22Z	Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing	Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling	X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	Robust Circuit Design for Flexible Electronics	T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	A self-testing and calibration method for embedded successive approximation register ADC	X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	Broadcast test pattern generation considering skew-insertion and partial-serial scan	C.-J. Lin; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs	W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager	X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:07Z	An Error Tolerance Scheme for 3D CMOS Imagers	H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:07Z	A scalable quantitative measure of IR-drop for scan pattern generation	M.-F. Wu;K.-H. Tsai;W.-T. Cheng;H.-C. Pan;J.-L. Huang;A. Kifli; M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:07Z	Power supply noise reduction in broadcast-based compression environment for at-speed scan testing	C.-Y. Liang;M.-F. Wu;J.-L. Huang; C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:06Z	An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation	M.-F. Wu;H.-C. Pan;T.-H. Wang;J.-L. Huang;K.-H. Tsai;W.-T. Cheng; M.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:06Z	A robust ADC code hit counting technique	J.-L. Huang;Kuo-Yu Chou;Ming-Huan Lu;Xuan-Lun Huang; J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:06Z	3D-PIC: An Error Tolerant 3D CMOS Imager	H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method	K.-W. Yeh;M.-F. Wu;J.-L. Huang; K.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	A Self-Testing Assisted Pipelined-ADC Calibration Technique	J.-L. Huang;X.-L. Huang;P.-Y. Kang; J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing	C.-Y. Yang;X.-L. Huang;J.-L. Huang; C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input	X.-L. Huang;C.-Y. Yang;J.-L. Huang; X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment	M.-F. Wu;J.-L. Huang;X. Wen;K. Miyase; M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	LPTest: A Flexible Low-Power Test Pattern Generator	M.-F. Wu;K.-S. Hu;J.-L. Huang; M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Specification back-propagation and its application to fault simulation of analog/mixed-signal circuits	J. L. Huang; C. Y. Pan; K. T. (Tim) Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input	X.-L. Huang;Y.-C. Yu;J.-L. Huang; X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:02Z	Ch. 8 Logic and Circuit Simulation	J.-L. Huang;C.-K. Koh;S. F. Cauley; J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing	M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry	J.-J. Huang;J.-L. Huang; J.-J. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment	Y.-T. Lin;M.-F. Wu;J.-L. Huang; Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization	P.-H. Chiu;J.-L. Huang; P.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	A Self-Testing and Calibration Technique for Current-Steering DACs	Y.-L. Ma; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	Design of a Fault Tolerant Carry Lookahead Adder	C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing	T.-L. Hung; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	An Efficient Peak Power Reduction Technique for Scan Testing	M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A routability constrained scan chain ordering technique for test power reduction	X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A period tracking based on-chip sinusoidal jitter extraction technique	C.-Y. Kuo; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing	S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG

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