|
English
|
正體中文
|
简体中文
|
0
|
|
???header.visitor??? :
52836308
???header.onlineuser??? :
823
???header.sponsordeclaration???
|
|
|
|
???tair.name??? >
???browser.page.title.author???
|
"kan t c"???jsp.browse.items-by-author.description???
Showing items 1-6 of 6 (1 Page(s) Totally)
1
View [10|25|50] records per page
| 國立臺灣科技大學 |
2015 |
Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration
|
Kan, T.-C.;Ruan, S.-J.;Chang, T.-F.;Yang, S.-H. |
| 國立臺灣科技大學 |
2014 |
Rule-based redundant via-aware standard cell design considering multiple via configuration
|
Kan, T.-C.;Chen, Y.-J.;Hong, H.-M.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2013 |
Configurable redundant via-aware standard cell design considering multi-via mechanism
|
Kan, T.-C.;Hong, H.-M.;Chen, Y.-J.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2013 |
Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning
|
Hsu, C.-H.;Ruan, S.-J.;Chen, Y.-J.;Kan, T.-C. |
| 國立臺灣科技大學 |
2013 |
Design of a practical nanometer-scale redundant via-aware standard cell library for improved redundant via1 insertion rate
|
Kan, T.-C.;Yang, S.-H.;Chang, T.-F.;Ruan, S.-J. |
| 國立臺灣科技大學 |
2010 |
A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes
|
Ruan S.-J.; Kan T.-C.; Hsu J.-C. |
Showing items 1-6 of 6 (1 Page(s) Totally)
1
View [10|25|50] records per page
|
