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"kuo j b"的相關文件
顯示項目 71-80 / 128 (共13頁)
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| 國立臺灣大學 |
1994-08 |
A 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSI
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Chen, Y.G.; Kuo, J.B. |
| 國立臺灣大學 |
1994-07 |
A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI
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Kuo, J.B.; Chen, B.Y.; Mao, M.W. |
| 臺大學術典藏 |
1994-07 |
A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI
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Kuo, J.B.; Chen, B.Y.; Mao, M.W.; Kuo, J.B.; Chen, B.Y.; Mao, M.W.; KuoJB |
| 國立臺灣大學 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
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Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB |
| 國立臺灣大學 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S. |
| 臺大學術典藏 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB |
| 國立臺灣大學 |
1994-02 |
Closed-form physical model for VLSI bipolar devices considering energy transport
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Kuo, J.B.; Huang, H.J.; Lu, T.C. |
| 臺大學術典藏 |
1994-02 |
Closed-form physical model for VLSI bipolar devices considering energy transport
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Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB |
| 國立臺灣大學 |
1994-01 |
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
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Kuo, J.B.; Wang, J.Y.; Chen, Y.G. |
顯示項目 71-80 / 128 (共13頁)
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