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Showing items 76-85 of 128 (13 Page(s) Totally)
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| 國立臺灣大學 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S. |
| 臺大學術典藏 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
|
Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB |
| 國立臺灣大學 |
1994-02 |
Closed-form physical model for VLSI bipolar devices considering energy transport
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Kuo, J.B.; Huang, H.J.; Lu, T.C. |
| 臺大學術典藏 |
1994-02 |
Closed-form physical model for VLSI bipolar devices considering energy transport
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Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB |
| 國立臺灣大學 |
1994-01 |
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
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Kuo, J.B.; Wang, J.Y.; Chen, Y.G. |
| 臺大學術典藏 |
1994-01 |
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
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Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; KuoJB |
| 國立臺灣大學 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 國立臺灣大學 |
1993-11 |
Amorphous silicon TFT capacitance model using an effective temperature approach
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Kuo, J.B.; Chen, S.S. |
| 臺大學術典藏 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1993-11 |
Amorphous silicon TFT capacitance model using an effective temperature approach
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Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB |
Showing items 76-85 of 128 (13 Page(s) Totally)
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