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"kuo po yi"的相关文件
显示项目 11-20 / 41 (共5页)
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| 國立交通大學 |
2019-04-02T05:58:50Z |
Investigation of low operation voltage InZnSnO thin-film transistors with different high-k gate dielectric by physical vapor deposition
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Kan, Kai-Zhi; Yu, Min-Chin; Chien, Ta-Chun; Chen, Yi-Heng; Kuo, Po-Yi; Sze, Simon M. |
| 國立交通大學 |
2018-08-21T05:56:29Z |
High Mobility Tungsten-Doped Thin-Film Transistor on Polyimide Substrate with Low Temperature Process
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Yu, Min-Chin; Gan, Kai-jhih; Chien, Ta-Chun; Kuo, Po-Yi; Sze, Simon M. |
| 國立交通大學 |
2018-08-21T05:54:11Z |
Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs
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Hsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:29Z |
Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs
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Hsieh, Dong-Ru; Chan, Yi-De; Kuo, Po-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:29Z |
Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity
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Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Lee, Sen-Yang; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:27Z |
Effects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film Transistors
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Liu, Po-Tsun; Chang, Chih-Hsiang; Kuo, Po-Yi; Chen, Po-Wen |
| 國立交通大學 |
2018-08-21T05:53:19Z |
Mobility enhancement for high stability tungsten-doped indium-zinc oxide thin film transistors with a channel passivation layer
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Kuo, Po-Yi; Yu, Min-Chin; Gan, Kai-Jhih; Chien, Ta-Chun; Sze, Simon M. |
| 國立交通大學 |
2017-04-21T06:56:35Z |
High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique
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Hsieh, Dong-Ru; Kuo, Po-Yi; Lin, Jer-Yi; Chen, Yi-Hsuan; Chang, Tien-Shun; Chao, Tien-Sheng |
| 國立交通大學 |
2017-04-21T06:56:21Z |
Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
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Lin, Jer-Yi; Kuo, Po-Yi; Lin, Ko-Li; Chin, Chun-Chieh; Chao, Tien-Sheng |
| 國立交通大學 |
2017-04-21T06:55:58Z |
High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET
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Hsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng |
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