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| 國立臺灣大學 |
1989-05 |
An upper-bound algorithm for gate-level delay analysis
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Lu, Sunshin; Lai, Feipei |
| 國立臺灣大學 |
1989-05 |
A grouping heuristic algorithm for gate matrix layout
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Liu, Jongping; Lai, Feipei |
| 國立臺灣大學 |
1989-05 |
MARS-Multiprocessor architecture reconciling symbolic with numerical processing-a CPU ensemble with zero-delay branch/jump
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Jang, Gia-Shuh; Lai, Feipei; Lee, Hung-Chang; Maa, Yeong-Chang; Parng, Tai-Ming; Tsai, Jenn-Yuan |
Showing items 251-253 of 253 (11 Page(s) Totally)
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