English  |  正體中文  |  简体中文  |  總筆數 :0  
造訪人次 :  52522943    線上人數 :  1147
教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
關於TAIR

瀏覽

消息

著作權

相關連結

"mri aryadeep"的相關文件

回到依作者瀏覽
依題名排序 依日期排序

顯示項目 1-12 / 12 (共1頁)
1 
每頁顯示[10|25|50]項目

機構 日期 題名 作者
亞洲大學 2015-04 Optimization of Holding Voltage for 5V Multi-Finger NMOS Using Voltage Mri, Aryadeep;Mrinal, Aryadeep
亞洲大學 2015-04 Optimization of Holding Voltage for 5V multi-finger NMOS using Voltage stepping simulation Mri, Aryadeep;Mrinal, Aryadeep
亞洲大學 2015-03 High Voltage NLDMOS with Multiple-RESURF Structure to Achieve Improved On-resistance 楊紹明;Yang, Shao-Ming;*; Hema, EP;Hema, EP;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;陳柏安;Chen, PA
亞洲大學 2015-03 A HSPICE Macro Model for the ESD Behavior of Gate Grounded NMOS and Gate coupled NMOS 楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;許健;Sheu, Gene;Mri, Aryadeep;Mrinal, Aryadeep;Md.Amanulla;Md.Amanullah;陳柏安;Chen, PA
亞洲大學 2015-03 High Voltage NLDMOS with Multiple-RESURF Structure to Achieve Improved On-resistance 楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;陳柏安;Chen, PA
亞洲大學 2015-03 A HSPICE Macro Model for the ESD Behavior of Gate Grounded NMOS and Gate coupled NMOS 楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;許健;Sheu, Gene;Mri, Aryadeep;Mrinal, Aryadeep;Md.Amanulla;Md.Amanullah;陳柏安;Chen, PA
亞洲大學 2014-01 Optimization of SiC Schottky Diode using Linear P-top for Edge Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek N, Man;Vivek N, Manjunatha M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming
亞洲大學 201310 Optimization of SiC Schottky Diode using Linear P for Edge Termination Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek, N;Vivek, N;Manjunatha, M;Manjunatha, M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming
亞洲大學 201310 Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep
亞洲大學 201310 Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology Kumar, Ankit;Kumar, Ankit;Yulia, Emita;Hapsari, Emita Yulia;Kuma, Vasanth;Kumar, Vasanth;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Ningar, Vivek;Ningaraju, Vivek
亞洲大學 2013-10 Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep
亞洲大學 2013-10 Optimization of SiC Schottky Diode using Linear P for Edge Termination Mri, Aryadeep;Aryadeep Mrinal, ;Kumar, Vijay;Vijay Kumar M P, ;Vivek N, ;Vivek N, ;Manjunatha, M;Manjunatha M, ;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming

顯示項目 1-12 / 12 (共1頁)
1 
每頁顯示[10|25|50]項目