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"pan c s"
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| 臺大學術典藏 |
2020-06-29T01:20:10Z |
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
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Chiang, K.-Y.;Ho, Y.-H.;Chen, Y.-W.;Pan, C.-S.;Li, J.C.-M.; Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:10Z |
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
|
Chiang, K.-Y.;Ho, Y.-H.;Chen, Y.-W.;Pan, C.-S.;Li, J.C.-M.; Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; Li, J.C.-M.; CHIEN-MO LI |
Showing items 1-2 of 2 (1 Page(s) Totally)
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