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"ruan shanq jang"的相關文件
顯示項目 1-22 / 22 (共1頁)
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| 臺大學術典藏 |
2021-11-21T23:19:18Z |
Development and Feasibility of a Kinect-Based Constraint-Induced Therapy Program in the Home Setting for Children With Unilateral Cerebral Palsy
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HAO-LING CHEN; Lin, Szu Yu; Yeh, Chun Fu; Chen, Ren Yu; Tang, Hsien Hui; Ruan, Shanq Jang; TIEN-NI WANG |
| 臺大學術典藏 |
2018-09-10T04:15:44Z |
Energy Analysis of Bipartition Architecture for Pipelined Circuits
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Ruan, Shanq-Jang;Naroska, Edwin;Chang, Yen-Ren;Ho, Chia-Lin;Lai, Feipei; Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Ren; Ho, Chia-Lin; Lai, Feipei; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:15:43Z |
Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits
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Ruan, Shanq-Jang; Ho, Chia-Lin; Naroska, Edwin; Lai, Feipei; FEI-PEI LAI |
| 國立臺灣大學 |
2006 |
Low Power Scheduling Method using Multiple Supply Voltages
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Tsai, Kun-Lin; Lee, Ju-Yueh; Ruan, Shanq-Jang; Lai, Feipei |
| 臺大學術典藏 |
2005-06 |
Optimal Permutation and Spacing for Unbiased Random, Counter, and Instruction Address Buses
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Naroska, Edwin; Ruan, Shanq-Jang; Uwe Schwiegelshohn; Lai, Feipei; FEI-PEI LAI |
| 國立臺灣大學 |
2005-05 |
A low power scheduling method using dual V/sub dd/ and dual V/sub th/
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Tsai, Kun-Lin; Chang, Szu-Wei; Lai, Feipei; Ruan, Shanq-Jang |
| 國立臺灣大學 |
2005 |
Bipartitioning and encoding in low-power pipelined circuits
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Ruan, Shanq-Jang; Tsai, Kun-Lin; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2005 |
Low Power Dynamic Bus Encoding for Deep Sub-micron Design
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Tsai, Kun-Lin; Ruan, Shanq-Jang; Chen, Li-Wei; Lai Feipei; Naroska, Edwin |
| 國立臺灣大學 |
2005 |
Optimal Permutation and Spacing for Unbiased Random, Counter, and Instruction Address Buses
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Naroska, Edwin; Ruan, Shanq-Jang; Uwe Schwiegelshohn; Lai, Feipei |
| 國立臺灣大學 |
2004 |
Circuit Partition and Reordering Technique for Low Power IP
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Tsai, Kun-Lin; Ruan, Shanq-Jang; Huang, Chun-Ming; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2003 |
Design and Analysis of Low Power Cache using Two-Level Filter Scheme
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Chang, Yen-Jen; Ruan, Shanq-Jang; Lai, Feipei |
| 國立臺灣大學 |
2002-10 |
Energy analysis of bipartition architecture for pipelined circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Ren; Ho, Chia-Lin; Lai, Feipei |
| 國立臺灣大學 |
2002-09 |
Cache design for eliminating the address translation bottleneck and reducing the tag area cost
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Chang, Yen-Jen; Lai, Feipei; Ruan, Shanq-Jang |
| 國立臺灣大學 |
2002-09 |
Power analysis of bipartition and dual-encoding architecture for pipelined circuits
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Ruan, Shanq-Jang; Ho, Chia-Lin; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2002 |
ENPCO: An Entropy-Based Partition-Codec Algorithm to Reduce Power for bipartition-codec architecture in Pipelined Circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Jen; Lai, Feipei; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001-05 |
Synthesis of partition-codec architecture for low power and small area circuit design
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Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Tsai, Kun-Lin; Lai, Feipei |
| 國立臺灣大學 |
2001-05 |
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture
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Chen, Po-Hung; Ruan, Shanq-Jang; Wu, Kuen-Pin; Hu, Dai-Xun; Lai, Feipei; Tsai, Kun-Lin |
| 國立臺灣大學 |
2001 |
Hierarchical Access Control Using the Secure Filter
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Wu, Kuen-Pin; Ruan, Shanq-Jang; Tseng, Chih-Kuang; Lai, Feipei |
| 國立臺灣大學 |
2001 |
A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits
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Ruan, Shanq-Jang; Shang, Rung-Ji; Lai, Feipei; Tsai, Kun-Lin |
| 國立臺灣大學 |
2000-12 |
An effective output-oriented algorithm for low power multipartition architecture
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Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Lai, Feipei; Tsai, Kun-Lin; Yu, Chung-Wei |
| 國立臺灣大學 |
2000-11 |
On key distribution in secure multicasting
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Wu, Kuen-Pin; Ruan, Shanq-Jang; Lai, Feipei; Tseng, Chih-Kuang |
| 國立臺灣大學 |
1999-11 |
A bipartition-codec architecture to reduce power in pipelined circuits
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Ruan, Shanq-Jang; Shang, Rung-Ji; Lai, Feipei; Chen, Shyh-Jong; Huang, Xian-Jun |
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