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| 國立交通大學 |
2019-04-02T06:04:51Z |
MapReduce-Based Pattern Classification for Design Space Analysis
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Wu, Yan-Shiun; Su, Hong-Yan; Chang, Yi-Hsiang; Topaloglu, Rasit Onur; Li, Yih-Lang |
| 國立交通大學 |
2018-08-21T05:57:11Z |
Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs
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Su, Hong-Yan; Nishizawa, Shinichi; Wu, Yan-Shiun; Shiomi, Jun; Li, Yih-Lang; Onodera, Hidetoshi |
| 國立交通大學 |
2018-08-21T05:57:01Z |
Clock Tree Aware Post-Global Placement Optimization
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Su, Hong-Yan; Chiang, Po-Ting; Samanta, Radhamanjari; Li, Yih-Lang |
| 國立交通大學 |
2017-04-21T06:48:48Z |
SubHunter: A High-Performance and Scalable Sub-Circuit Recognition Method with Prufer-Encoding
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Su, Hong-Yan; Hsu, Chih-Hao; Li, Yih-Lang |
| 國立交通大學 |
2015-07-21T08:28:45Z |
A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prufer Encoding
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Su, Hong-Yan; Chen, Chieh-Chu; Li, Yih-Lang; Tu, An-Chun; Wu, Chuh-Jen; Huang, Chen-Ming |
| 國立交通大學 |
2014-12-12T02:33:33Z |
使用Prüfer序列的佈局編碼技術的精準快速之製程熱點偵測技術
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蘇宏彥; Su, Hong-Yan; 李毅郎; Li, Yih-Lang |
Showing items 1-6 of 6 (1 Page(s) Totally)
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