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Institution	Date	Title	Author
臺大學術典藏	2019-10-24T08:27:13Z	A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor�VSharing Technique for Thermoelectric Energy Harvesting Applications	TAI-CHENG LEE;T-C Lee;C-L Chang; C-L Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:26:16Z	An 84.7-DR Wide BW Incremental ADC	T-Y Wang;T-C Lee; T-Y Wang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:26:16Z	A Single-Channel 10-b 400-MS/s 8.7-mW Pipeline ADC in a 90-nm Technology	C-K Hsu;T-C Lee; C-K Hsu; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise	P-C Huang;W-S Chang;T-C Lee; P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise	P-C Huang;W-S Chang;T-C Lee; P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth	J-A Cheng;W-S Chang;T-C Lee; J-A Cheng; W-S Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator	Y-H Kang;C-Y Lin;T-C Lee; Y-H Kang; C-Y Lin; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique	C-Y Lin;T-C Lee; C-Y Lin; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 6-Gb/s Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuits	L-H Chiueh;T-C Lee; L-H Chiueh; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A Compact Multi-Input Thermoelectric Energy Harvesting System with 58.5% Power Conversion Efficiency and 32.4-mW Output Power Capability	C-L Chang;T-C Lee; C-L Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	Circuit for spread spectrum transmission and method thereof	T-C Lee;C-W Wong; T-C Lee; C-W Wong; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:40Z	2.4-GHz High-Efficiency Adaptive Power Harvester	C-C Lee;T-C Lee; C-C Lee; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:50:53Z	A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator	C-H Wong;T-C Lee; C-H Wong; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:50:53Z	Jitter Error Cancellation Technique in Digital Domain for ADC	C-Y Lin;T-C Lee; C-Y Lin; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:50:53Z	Analysis of the Leakage Effect in a Pipelined ADC with Nanoscale CMOS Technologies	C-Y Lin Y-C Huang;T-C Lee; C-Y Lin Y-C Huang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:50:53Z	Pipelined analog-to-digital converter and method for converting analog signal to digital signal,	Y-C Huang;T-C Lee; Y-C Huang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:25:30Z	A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG)	C-D Su;C-W Lee;T-C Lee; C-D Su; C-W Lee; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:25:30Z	A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter	C-C Ho;T-C Lee; C-C Ho; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	The Study of a Dual-Mode Ring Oscillator	Z-Z Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	The Design and Analysis of Dual-Delay-Path Ring Oscillators	Z-Z Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS	P Zhang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Method for achieving high-speed analog-to-digital conversion without degrading accuracy, and associated apparatus	L-H Hung; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Digital-to-analog converter (DAC) and an associated method	T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	Nonlinear R-2R Transistor-Only DAC	T-C Lee;C-H Lin; T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques	Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques	Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques	Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III	C-Y Lin;C-Y Chiang;T-C Lee; C-Y Lin; C-Y Chiang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay	Y-C Hung;K Fong;T-C Lee; Y-C Hung; K Fong; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	An All‐Digital De‐skew Clock Generator for Arbitrary Wide Range Delay	K Fong;Z-Z Chen;T-C Le; K Fong; Z-Z Chen; T-C Le; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB	K-T Chen;T-C Lee; K-T Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification	Feng-Chiu Hsieh;Tai-Cheng; Feng-Chiu Hsieh; Tai-Cheng; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:31Z	A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning	K-J Hsiao; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:37:54Z	A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning	K-J Hsiao; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:37:53Z	A Delay-Line-Based GFSK Demodulator for Low-IF Receivers	H-S Kao; M-J Yang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:03:18Z	A Spur-Suppression Technique for Phase-Locked Frequency Synthesizers	W.-L. Lee; TAI-CHENG LEE; T.-C. Lee
臺大學術典藏	2018-09-10T06:03:17Z	A Mixed-Signal GFSK Demodulator for Bluetooth	T.-C. Lee; C.-C. Chen; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:03:17Z	The design and analysis of a Miller Divider Based Clock Generator for MBOA-UWB Application	T.-C. Lee; Y.-C. Huang; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:03:17Z	The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application	T.-C. Lee; K.-J. Hsiao; TAI-CHENG LEE
臺大學術典藏	2018-09-10T05:29:20Z	A Linear-Approximation Technique for Digitally-Calibrated Pipelined ADCs	D. L. Shen; T. C. Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T05:29:20Z	An Optimization Technique for RF Buffers with Active Inductors	T. C. Lee; Y. C. Huang; TAI-CHENG LEE

Showing items 21-70 of 77 (2 Page(s) Totally)
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