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Showing items 11-16 of 16 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:36:49Z |
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications
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Cheng, Chung-Chao; Yang, Jeng-Da; Lee, Huang-Chang; Yang, Chia-Hsiang; Ueng, Yeong-Luh |
| 國立臺灣大學 |
2010 |
Interblock Memory for Turbo Coding
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Yeh, Chia-Jung; Ueng, Yeong-Luh; Lin, Mao-Chao; Lu, Ming-Che |
| 國立臺灣大學 |
2009 |
Turbo Coded Multiple-Antenna Systems for Near-Capacity Performance
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Ueng, Yeong-Luh; Yeh, Chia-Jung; Lin, Mao-Chao; Wang, Chung-Li |
| 國立臺灣大學 |
2008 |
Low-Density Parity-Check Coded Recording Systems With Run-Length-Limited Constraints
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Chen, Hsin-Yi; Lin, Mao-Chao; Ueng, Yeong-Luh |
| 國立臺灣大學 |
2002 |
On Trellis Codes With a Delay Processor and a Signal Mapper
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Ueng, Yeong-Luh; Yeh, Chia-Jung; Lin, Mao-Chao |
| 國立臺灣大學 |
2000 |
Two Trellis Coding Schemes for Large Free Distance
|
Lin, Mao-Chao; Ueng, Yeong-Luh; Wang, Jia-Yin |
Showing items 11-16 of 16 (1 Page(s) Totally)
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