| 國立交通大學 |
2014-12-08T15:41:16Z |
Hierarchical Architecture for Network-on-Chip Platform
|
Lin, Liang-Yu; Lin, Huang-Kai; Wang, Cheng-Yeh; Van, Lan-Da; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:37:51Z |
Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures
|
Chen, Pei-Yu; Van, Lan-Da; Khoo, I-Hung; Reddy, Hari C.; Lin, Chin-Teng |
| 國立交通大學 |
2014-12-08T15:36:28Z |
General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry
|
Khoo, I. -Hung; Reddy, Hari C.; Van, Lan-Da; Lin, Chin-Teng |
| 國立交通大學 |
2014-12-08T15:27:15Z |
A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System
|
Van, Lan-Da; Sheu, Ten-Yao |
| 國立交通大學 |
2014-12-08T15:24:50Z |
A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application
|
Lin, Chin-Teng; Yu, Yuan-Chu; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:23:27Z |
Low Complexity Subdivision Algorithm to Approximate Phong Shading Using Forward Difference
|
Sheu, Teng-Yao; Van, Lan-Da; Jung, Tzung-Rung; Lin, Cheng-Wei; Chang, Ting-Wei |
| 國立交通大學 |
2014-12-08T15:20:29Z |
A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications
|
Lu, Tsung-Che; Van, Lan-Da; Lin, Chi-Sheng; Huang, Chun-Ming |
| 國立交通大學 |
2014-12-08T15:19:53Z |
A New VLSI 2-D Fourfold-Rotational-Symmetry Filter Architecture Design
|
Chen, Pei-Yu; Van, Lan-Da; Reddy, Hari C.; Lin, Chin-Teng |
| 國立交通大學 |
2014-12-08T15:13:51Z |
Adaptive low-error fixed-width booth multipliers
|
Song, Min-An; Van, Lan-Da; Kuo, Sy-Yen |
| 國立交通大學 |
2014-12-08T15:12:02Z |
Efficient Detection Algorithms for MIMO Communication Systems
|
Wu, Di-You; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:11:08Z |
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
|
Lin, Chin-Teng; Yu, Yuan-Chu; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:09:30Z |
Classification of driver's cognitive responses using nonparametric single-trial EEG analysis
|
Lin, Chin-Teng; Ko, Li-Wei; Lin, Ken-Li; Kuo, Bor-Chen; Liang, Sheng-Fu; Chung, I-Fang; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:08:34Z |
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
|
Tu, Jin-Hao; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:05:45Z |
VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design
|
Van, Lan-Da; Lin, Chin-Teng; Yu, Yuan-Chu |
| 國立交通大學 |
2014-12-08T15:04:15Z |
Design of Multi-Mode Depth Buffer Compression for 3D Graphics System
|
Jung, Tzung-Rung; Van, Lan-Da; Sheu, Teng-Yao; Lin, Cheng-Wei; Fang, Wai-Chi |
| 國立交通大學 |
2014-12-08T15:02:18Z |
Reconfigurable depth buffer compression design for 3D graphics system
|
Jung, Tzung-Rung; Van, Lan-Da; Fang, Wai-Chi; Shen, Teng-Yao |
| 國立臺灣大學 |
2007 |
Adaptive Low-Error Fixed-Width Booth Multipliers
|
Song, Min-An; Van, Lan-Da; Kuo, Sy-Yen |
| 國立臺灣大學 |
2005-06 |
Hardware-efficient architecture design of wavelet-based adaptive visible watermarking
|
Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai |
| 臺大學術典藏 |
2005-06 |
Hardware-efficient architecture design of wavelet-based adaptive visible watermarking
|
Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai; Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai |
| 國立臺灣大學 |
2005-05 |
A framework for the design of error-aware power-efficient fixed-width Booth multipliers
|
Song, Min-An; Van, Lan-Da; Yang, Chih-Chyau; Chiu, Shih-Chieh; Kuo, Sy-Yen |
| 國立臺灣大學 |
2004-07 |
A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers
|
Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 臺大學術典藏 |
2004-07 |
A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers
|
Kuo, Sy-Yen; Huang, Ting-Chun; Van, Lan-Da; Song, Min-An; Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 國立臺灣大學 |
2003-12 |
A low-error and area-time efficient fixed-width booth multiplier
|
Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 臺大學術典藏 |
2003-12 |
A low-error and area-time efficient fixed-width booth multiplier
|
Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen; Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 國立臺灣大學 |
2001-05 |
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage
|
Tang, Chih-Chun; Lu, Wen-Shih; Van, Lan-Da; Feng, Wu-Shiung |
| 國立臺灣大學 |
2000-12 |
Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters
|
Van, Lan-Da; Feng, Wu-Shiung |
| 國立臺灣大學 |
2000-12 |
A new 2-D digital filter using a locally broadcast scheme and its cascade form
|
Van, Lan-Da; Shing, Tenqchen; Chang, Chi-Hong; Feng, Wu-Shiung |
| 國立臺灣大學 |
2000-05 |
A new VLSI architecture without global broadcast for 2-D digital filters
|
Van, Lan-Da; Tang, Chih-Chun; Shing,Tenqchen; Feng, Wu-Shiung |
| 國立臺灣大學 |
1999-06 |
Design of a lower-error fixed-width multiplier for speech processing application
|
Van, Lan-Da; Wang, Shuenn-Shyang; Tenqchen, Shing; Feng, Wu-Shiung; Jeng, Bor-Shenn |
| 國立臺灣大學 |
1999-03 |
A tree-systolic array of DLMS adaptive filter
|
Van, Lan-Da; Tenqchen, Shing; Chang, Chia-Hsun; Feng, Wu-Shiung |
