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"van lan da"的相關文件
顯示項目 81-100 / 100 (共4頁)
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| 國立交通大學 |
2014-12-08T15:11:08Z |
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
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Lin, Chin-Teng; Yu, Yuan-Chu; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:09:30Z |
Classification of driver's cognitive responses using nonparametric single-trial EEG analysis
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Lin, Chin-Teng; Ko, Li-Wei; Lin, Ken-Li; Kuo, Bor-Chen; Liang, Sheng-Fu; Chung, I-Fang; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:08:34Z |
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
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Tu, Jin-Hao; Van, Lan-Da |
| 國立交通大學 |
2014-12-08T15:05:45Z |
VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design
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Van, Lan-Da; Lin, Chin-Teng; Yu, Yuan-Chu |
| 國立交通大學 |
2014-12-08T15:04:15Z |
Design of Multi-Mode Depth Buffer Compression for 3D Graphics System
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Jung, Tzung-Rung; Van, Lan-Da; Sheu, Teng-Yao; Lin, Cheng-Wei; Fang, Wai-Chi |
| 國立交通大學 |
2014-12-08T15:02:18Z |
Reconfigurable depth buffer compression design for 3D graphics system
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Jung, Tzung-Rung; Van, Lan-Da; Fang, Wai-Chi; Shen, Teng-Yao |
| 國立臺灣大學 |
2007 |
Adaptive Low-Error Fixed-Width Booth Multipliers
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Song, Min-An; Van, Lan-Da; Kuo, Sy-Yen |
| 國立臺灣大學 |
2005-06 |
Hardware-efficient architecture design of wavelet-based adaptive visible watermarking
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Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai |
| 臺大學術典藏 |
2005-06 |
Hardware-efficient architecture design of wavelet-based adaptive visible watermarking
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Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai; Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai |
| 國立臺灣大學 |
2005-05 |
A framework for the design of error-aware power-efficient fixed-width Booth multipliers
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Song, Min-An; Van, Lan-Da; Yang, Chih-Chyau; Chiu, Shih-Chieh; Kuo, Sy-Yen |
| 國立臺灣大學 |
2004-07 |
A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers
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Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 臺大學術典藏 |
2004-07 |
A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers
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Kuo, Sy-Yen; Huang, Ting-Chun; Van, Lan-Da; Song, Min-An; Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 國立臺灣大學 |
2003-12 |
A low-error and area-time efficient fixed-width booth multiplier
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Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 臺大學術典藏 |
2003-12 |
A low-error and area-time efficient fixed-width booth multiplier
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Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen; Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen |
| 國立臺灣大學 |
2001-05 |
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage
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Tang, Chih-Chun; Lu, Wen-Shih; Van, Lan-Da; Feng, Wu-Shiung |
| 國立臺灣大學 |
2000-12 |
Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters
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Van, Lan-Da; Feng, Wu-Shiung |
| 國立臺灣大學 |
2000-12 |
A new 2-D digital filter using a locally broadcast scheme and its cascade form
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Van, Lan-Da; Shing, Tenqchen; Chang, Chi-Hong; Feng, Wu-Shiung |
| 國立臺灣大學 |
2000-05 |
A new VLSI architecture without global broadcast for 2-D digital filters
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Van, Lan-Da; Tang, Chih-Chun; Shing,Tenqchen; Feng, Wu-Shiung |
| 國立臺灣大學 |
1999-06 |
Design of a lower-error fixed-width multiplier for speech processing application
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Van, Lan-Da; Wang, Shuenn-Shyang; Tenqchen, Shing; Feng, Wu-Shiung; Jeng, Bor-Shenn |
| 國立臺灣大學 |
1999-03 |
A tree-systolic array of DLMS adaptive filter
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Van, Lan-Da; Tenqchen, Shing; Chang, Chia-Hsun; Feng, Wu-Shiung |
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