|
English
|
正體中文
|
简体中文
|
Total items :2856565
|
|
Visitors :
53391313
Online Users :
754
Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"wan w k"
Showing items 1-7 of 7 (1 Page(s) Totally) 1 View [10|25|50] records per page
| 臺大學術典藏 |
2021-09-02T00:04:00Z |
Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs
|
Chung C.-C;Ye H.-Y;Lin H.H;Wan W.K;Yang M.-T;Liu C.W.; Chung C.-C; Ye H.-Y; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU |
| 臺大學術典藏 |
2021-09-02T00:04:00Z |
Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs
|
Chung C.-C;Ye H.-Y;Lin H.H;Wan W.K;Yang M.-T;Liu C.W.; Chung C.-C; Ye H.-Y; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU |
| 臺大學術典藏 |
2021-09-02T00:03:56Z |
Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry
|
Chung C.-C;Lin H.-C;Lin H.H;Wan W.K;Yang M.-T;Liu C.W.; Chung C.-C; Lin H.-C; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU |
| 臺大學術典藏 |
2021-09-02T00:03:56Z |
Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry
|
Chung C.-C;Lin H.-C;Lin H.H;Wan W.K;Yang M.-T;Liu C.W.; Chung C.-C; Lin H.-C; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU |
| 臺大學術典藏 |
2021-09-02T00:03:51Z |
Comprehensive thermal SPICE modeling of FinFETs and BEOL with layout flexibility considering frequency dependent thermal time constant, 3D heat flows, boundary/alloy scattering, and interfacial thermal resistance with circuit level reliability evaluation
|
Yan J.-Y;Chung C.-C;Jan S.-R;Lin H.H;Wan W.K;Yang M.-T;Liu C.W.; Yan J.-Y; Chung C.-C; Jan S.-R; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU |
| 臺大學術典藏 |
2021-09-02T00:03:51Z |
Comprehensive thermal SPICE modeling of FinFETs and BEOL with layout flexibility considering frequency dependent thermal time constant, 3D heat flows, boundary/alloy scattering, and interfacial thermal resistance with circuit level reliability evaluation
|
Yan J.-Y;Chung C.-C;Jan S.-R;Lin H.H;Wan W.K;Yang M.-T;Liu C.W.; Yan J.-Y; Chung C.-C; Jan S.-R; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU |
| 臺大學術典藏 |
2021-01-19T12:08:32Z |
Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry
|
Chung, Chia Che; Lin, Hsin Cheng; Lin, H. H.; Wan, W. K.; Yang, M. T.; CHEN-WUING LIU |
Showing items 1-7 of 7 (1 Page(s) Totally) 1 View [10|25|50] records per page
|