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Showing items 1-10 of 10 (1 Page(s) Totally)
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| 臺大學術典藏 |
2020-05-04T07:27:39Z |
A hybrid DRAM/PCM buffer cache architecture for smartphones with QoS consideration
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Lin, Y.-J.;Yang, C.-L.;Li, H.-P.;Wang, C.-Y.M.; Lin, Y.-J.; Yang, C.-L.; Li, H.-P.; Wang, C.-Y.M.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T15:32:51Z |
Improving PCM endurance with a constant-cost wear leveling design
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Chang, Y.-M.; Hsiu, P.-C.; Chang, Y.-H.; Chen, C.-H.; Kuo, T.-W.; Wang, C.-Y.M.; Chang, Y.-M.; Hsiu, P.-C.; Chang, Y.-H.; Chen, C.-H.; Kuo, T.-W.; Wang, C.-Y.M.; TEI-WEI KUO |
| 臺大學術典藏 |
2018-09-10T15:32:51Z |
Improving PCM endurance with a constant-cost wear leveling design
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Chang, Y.-M.; Hsiu, P.-C.; Chang, Y.-H.; Chen, C.-H.; Kuo, T.-W.; Wang, C.-Y.M.; Chang, Y.-M.; Hsiu, P.-C.; Chang, Y.-H.; Chen, C.-H.; Kuo, T.-W.; Wang, C.-Y.M.; TEI-WEI KUO |
| 臺大學術典藏 |
2018-09-10T15:21:13Z |
SECRET: A selective error correction framework for refresh energy reduction in DRAMs
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Lin, C.-H.;Shen, D.-Y.;Chen, Y.-J.;Yang, C.-L.;Wang, C.-Y.M.; Lin, C.-H.; Shen, D.-Y.; Chen, Y.-J.; Yang, C.-L.; Wang, C.-Y.M.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T15:21:13Z |
SECRET: A selective error correction framework for refresh energy reduction in DRAMs
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Lin, C.-H.;Shen, D.-Y.;Chen, Y.-J.;Yang, C.-L.;Wang, C.-Y.M.; Lin, C.-H.; Shen, D.-Y.; Chen, Y.-J.; Yang, C.-L.; Wang, C.-Y.M.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T14:56:02Z |
NVM Duet: Unified working memory and persistent store architecture
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Yu, S.-C.; Wang, C.-Y.M.; CHIA-LIN YANG; Liu, R.-S.;Shen, D.-Y.;Yang, C.-L.;Yu, S.-C.;Wang, C.-Y.M.; Liu, R.-S.; Shen, D.-Y.; Yang, C.-L. |
| 臺大學術典藏 |
2018-09-10T14:56:02Z |
NVM Duet: Unified working memory and persistent store architecture
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Yu, S.-C.; Wang, C.-Y.M.; CHIA-LIN YANG; Liu, R.-S.;Shen, D.-Y.;Yang, C.-L.;Yu, S.-C.;Wang, C.-Y.M.; Liu, R.-S.; Shen, D.-Y.; Yang, C.-L. |
| 臺大學術典藏 |
2018-09-10T09:20:18Z |
Age-based PCM wear leveling with nearly zero search cost
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Chen, C.-H.; Hsiu, P.-C.; Kuo, T.-W.; Yang, C.-L.; Wang, C.-Y.M.; TEI-WEI KUO; CHIA-LIN YANG |
| 臺大學術典藏 |
2015 |
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory
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Lin, Y.-J.;Yang, C.-L.;Li, H.-P.;Wang, C.-Y.M.; Lin, Y.-J.; Yang, C.-L.; Li, H.-P.; Wang, C.-Y.M.; CHIA-LIN YANG |
| 臺大學術典藏 |
2015 |
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory
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Lin, Y.-J.;Yang, C.-L.;Li, H.-P.;Wang, C.-Y.M.; Lin, Y.-J.; Yang, C.-L.; Li, H.-P.; Wang, C.-Y.M.; CHIA-LIN YANG |
Showing items 1-10 of 10 (1 Page(s) Totally)
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