| 國立交通大學 |
2014-12-16T06:15:47Z |
SILICON CONTROLLED RECTIFIER
|
Ker, Ming-Dou; Lin, Chun-Yu; Wang, Chang-Tzu |
| 國立交通大學 |
2014-12-16T06:15:37Z |
ESD PROTECTION CIRCUITRY WITH MULTI-FINGER SCRS
|
Ker, Ming-Dou; Lin, Chun-Yu; Wang, Chang-Tzu |
| 國立交通大學 |
2014-12-16T06:15:35Z |
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND RELATED CIRCUIT
|
Ker, Ming-Dou; Hsiao, Yuan-Wen; Wang, Chang-Tzu |
| 國立交通大學 |
2014-12-16T06:15:23Z |
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
|
Ker Ming-Dou; Lin Chun-Yu; Wang Chang-Tzu |
| 國立交通大學 |
2014-12-16T06:14:53Z |
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
|
Ker Ming-Dou; Lin Chun-Yu; Wang Chang-Tzu |
| 國立交通大學 |
2014-12-16T06:14:05Z |
ESD protection circuitry with multi-finger SCRS
|
Ker Ming-Dou; Lin Chun-Yu; Wang Chang-Tzu |
| 國立交通大學 |
2014-12-16T06:13:59Z |
Electrostatic discharge protection circuit
|
Ker Ming-Dou; Lin Chun-Yu; Wang Chang-Tzu |
| 國立交通大學 |
2014-12-12T01:22:36Z |
積體電路電源線間具低漏電流之靜電放電防護電路設計
|
王暢資; Wang, Chang-Tzu; 柯明道; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:38:25Z |
ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:18Z |
Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou; Tang, Tien-Hao; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:24:42Z |
Circuit Solutions on ESD Protection Design for Mixed-Voltage I/O Buffers in Nanoscale CMOS
|
Ker, Ming-Dou; Wang, Chang-Tzu |
| 國立交通大學 |
2014-12-08T15:15:11Z |
Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
|
Ker, Ming-Dou; Wang, Chang-Tzu; Tang, Tien-Hao; Su, Kuan-Cbeng |
| 國立交通大學 |
2014-12-08T15:09:50Z |
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:48Z |
Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
|
Ker, Ming-Dou; Wang, Chang-Tzu |
| 國立交通大學 |
2014-12-08T15:06:44Z |
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 義守大學 |
2009 |
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology
|
Wang, Chang-Tzu ; Ker, Ming-Dou ; Tang, Tien-Hao ; Su, Kuan-Cheng |
| 義守大學 |
1999-07 |
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS
|
Ker, Ming-Dou ; Wang, Chang-Tzu |
