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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-16T06:15:56Z |
Pre-charge sample-and-hold circuit
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Wu, Jieh-Tsorng; Lee, Zwei-Mei; Wang, Cheng-Yeh |
| 國立交通大學 |
2014-12-08T15:41:16Z |
Hierarchical Architecture for Network-on-Chip Platform
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Lin, Liang-Yu; Lin, Huang-Kai; Wang, Cheng-Yeh; Van, Lan-Da; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Communication-driven task binding for multiprocessor with latency insensitive Network-on-Chip
|
Lin, Liang-Yu; Wang, Cheng-Yeh; Huang, Pao-Jui; Chou, Chih-Chieh; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:24:43Z |
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration
|
Lee, Zwei-Mei; Wang, Cheng-Yeh; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:13:33Z |
Hybrid word-length optimization methods of pipelined FFT processors
|
Wang, Cheng-Yeh; Kuo, Chih-Bin; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:05:23Z |
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration
|
Lee, Zwei-Mei; Wang, Cheng-Yeh; Wu, Jieh-Tsorng |
| 東海大學 |
1994 |
液晶高分子之流變光學研究
|
王承業; Wang, Cheng-Yeh |
Showing items 1-7 of 7 (1 Page(s) Totally)
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