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Showing items 1-8 of 8 (1 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-11T06:33:09Z |
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking
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Wu, Cheng-Yin;Wu, Chi-An;Lai, Chien-Yu;Huang, Chung-Yang R.; Wu, Cheng-Yin; Wu, Chi-An; Lai, Chien-Yu; Huang, Chung-Yang R.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:09Z |
Interpolation-based incremental ECO synthesis for multi-error logic rectification.
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Tang, Kai-Fu;Wu, Chi-An;Huang, Po-Kai;Huang, Chung-Yang (Ric); Tang, Kai-Fu; Wu, Chi-An; Huang, Po-Kai; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:09Z |
Interpolant generation without constructing resolution graph.
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Hsu, Chih-Jen;Huang, Shao-Lun;Wu, Chi-An;Huang, Chung-Yang; Hsu, Chih-Jen; Huang, Shao-Lun; Wu, Chi-An; Huang, Chung-Yang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:07Z |
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method.
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Yeh, Yu-Fu;Huang, Chung-Yang;Wu, Chi-An;Lin, Hsin-Cheng; Yeh, Yu-Fu; Huang, Chung-Yang; Wu, Chi-An; Lin, Hsin-Cheng; CHUNG-YANG HUANG |
| 國立臺灣大學 |
2009 |
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
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Wu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang |
| 臺大學術典藏 |
2009 |
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
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Wu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang; Wu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang |
| 國立臺灣大學 |
2008 |
在電路上實現之布林函數解法器以及它在利用電路重新連線進行邏輯最佳化之應用
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吳濟安; Wu, Chi-An |
| 國立政治大學 |
1996 |
孔子與老子政治思想之比較研究——以無為而治論為主軸
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吳濟安; Wu, Chi-An |
Showing items 1-8 of 8 (1 Page(s) Totally)
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