| 國立交通大學 |
2020-07-01T05:21:48Z |
Construction of Delay-Driven GNR Routing Tree
|
Yan, Jin-Tai; Yen, Chia-Heng |
| 國立交通大學 |
2019-04-02T06:04:49Z |
Feasible Assignment of Micro-Bumps in 3D ICs
|
Yan, Jin-Tai; Yen, Chia-Heng |
| 國立交通大學 |
2017-04-21T06:49:38Z |
Timing-Constrained Yield-Driven Redundant Via Insertion
|
Yan, Jin-Tai; Chen, Zhi-Wei; Chiang, Bo-Yi; Lee, Yu-Min |
| 國立交通大學 |
2014-12-12T02:14:17Z |
在聚集晶元佈局上K-方電路分割,擺置改良,區域定義和繞線順序設計之設計
|
顏金泰; Yan, Jin Tai; 蕭培墉; Xiao, Pei Yong |
| 國立交通大學 |
2014-12-12T02:06:45Z |
一個(M+1)位元迴饋分割式通訊協定
|
顏金泰; YAN,JIN-TAI; 簡榮宏; JIAN,RONG-HONG |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model
|
Yan, Jin-Tai; Lin, Kai-Ping; Luo, Yue-Fong |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Optimal shielding insertion for inductive noise avoidance
|
Yan, Jin-Tai; Lin, Kuen-Ming; Chen, Yen-Hsiang |
| 國立交通大學 |
2014-12-08T15:02:59Z |
Block-Level Thermal Model for Floorplan Stage in VLSI Design Flow
|
Lin, Shun-Hua; Yan, Jin-Tai; Chiueh, Herming |
| 中華大學 |
2013 |
Routability-Constrained Multi-Bit Flip-Flop Construction for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Timing-Constrained Replacement Using Spare Cells for Design Changes
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Resource-Constrained Link Insertion for Delay Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Utilization of Multi-Bit Flip-Flops for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Top-Down-Based Symmetrical Buffered Clock Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Direction-Constrained Layer Assignment for Rectangle Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Timing-Constrained I/O Buffer Placement for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-Aware Length-Matching Bus Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Simultaneous Escape Routing Based on Routability-Driven Net Ordering
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Thermal Via Planning for Temperature Reduction in 3D ICs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Low-Cost Low-Power Bypassing-Based Multiplier Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-Driven Flip-Flop Merging Process for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-driven partitioning-based IO assignment for flip-chip designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-Driven RDL Routing with Pin Reassignment
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Two-Sided Single-Detour Untangling for Bus Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Ordered Escape Routing via Routability-Driven Pin Assignment
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Width-constrained Wire Sizing for Non-tree Interconnections
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Resource-Constrained Timing-Driven Link Insertion for Critical Delay Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Optimal Transformation of Non-tree Topologies for Timing Analysis
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Low-Power Multiplier Design with Row and Column Bypassing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
RDL Pre-assignment Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Construction of Constrained Multi-Bit Flip-Flops for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Accurate Transformation-Based Timing Analysis for RC Non-tree Circuits
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Redundant Wire Insertion for Yield Improvement
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
計算機組織與結構概論
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment and Path Reconstruction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Constrained Yield-driven Redundant Via Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Thermal-Driven White Space Redistribution for Block-Level Floorplans
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids
|
顏金泰; YAN, JIN-TAI |
