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Showing items 1-15 of 15 (1 Page(s) Totally)
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| 臺大學術典藏 |
2020-05-04T07:27:41Z |
Placement of digital microfluidic biochips using the t-tree formulation
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Yang, C.-L.; Chang, Y.-W.; CHIA-LIN YANG; Yuh, P.-H. |
| 臺大學術典藏 |
2020-05-04T07:27:40Z |
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
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CHIA-LIN YANG; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W. |
| 臺大學術典藏 |
2018-09-10T08:39:31Z |
A SAT-based routing algorithm for cross-referencing biochips
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Yuh, P.-H.;Lin, C.C.-Y.;Huang, T.-W.;Ho, T.-Y.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Lin, C.C.-Y.; Huang, T.-W.; Ho, T.-Y.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:36:57Z |
A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips
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Yuh, P.-H.;Sapatnekar, S.S.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
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Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:33:29Z |
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
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Yuh, P.-H.;Yang, C.-L.;Li, C.-F.;Lin, C.-H.; Yuh, P.-H.; Yang, C.-L.; Li, C.-F.; Lin, C.-H.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
MP-trees: A packing-based macro placement algorithm for modern mixed-size designs
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Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, T.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:01Z |
MP-trees: A packing-based macro placement algorithm for mixed-size designs
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Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:00Z |
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
|
Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T06:30:59Z |
Temporal floorplanning using the three-dimensional transitive closure subGraph
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Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
A routing algorithm for flip-chip design
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Fang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:20:42Z |
Joint exploration of architectural and physical design spaces with thermal consideration
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Wu, Y.-W.; Yang, C.-L.; Yuh, P.-H.; Chang, Y.-W.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using the T-tree formulation
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Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using 3D-subTCG
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Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.;Chen, H.-L.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG |
| 國立臺灣大學 |
2008 |
MP-trees: A packing-based macro placement algorithm for modern mixed-size designs
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Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D. |
Showing items 1-15 of 15 (1 Page(s) Totally)
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