| 國立臺灣科技大學 |
2009-04 |
Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator
|
Chia-Yu Yao;Chih-Chun Hsieh |
| 國立臺灣大學 |
2009 |
HARDWARE SOFTWARE CO-DESIGN OF A MULTIMEDIA SOC PLATFORM
|
Chen, Sao-Jie; Lin, Guang-Huei; Hsiung, Pao-Ann; Hu, Yu–Hen |
| 臺大學術典藏 |
2018-09-10T07:36:33Z |
Hardware software co-design of a multimedia SOC platform
|
Hu, Yu-Hen;Hsiung, Pao-Ann;Lin, Guang-Huei;Chen, Sao-Jie; Hu, Yu-Hen; Hsiung, Pao-Ann; Lin, Guang-Huei; Chen, Sao-Jie; Chen, Sao-Jie |
| 臺大學術典藏 |
1993-10 |
Hardware verification using symbolic state transition graphs
|
Chen, Pin-Hong; Shyu, Jyuo-Min; Chen, Liang-Gee; Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee |
| 國立臺灣大學 |
1993-10 |
Hardware verification using symbolic state transition graphs
|
Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:49Z |
Hardware verification using symbolic state transition graphs
|
Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2020-06-11T06:29:41Z |
Hardware Verification Using Symbolic State Transition Graphs.
|
Chen, Pinhong;Shyu, Jyuo-Min;Chen, Liang-Gee; Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2021-09-21T23:19:35Z |
Hardware- And Memory-Efficient Architecture for Disparity Estimation of Large Label Counts
|
Wu, Sih Sian; Chen, Hon Hui; LIANG-GEE CHEN |
| 臺大學術典藏 |
2020-05-04T08:04:29Z |
Hardware-accelerated cache simulation for multicore by FPGA
|
Hung, S.-H.; Ho, Y.-M.; Yeh, C.-W.; Cheng-Yueh, Lee, C.-P.; SHIH-HAO HUNG |
| 臺大學術典藏 |
2018 |
Hardware-accelerated cache simulation for multicore by FPGA.
|
SHIH-HAO HUNG; Lee, Chen-Pang; Liu, Cheng-Yueh; Yeh, Chih Wei; Ho, Yi-Mo; Hung, Shih-Hao |
| 朝陽科技大學 |
2019-08-23 |
Hardware-accelerated, Short-term Processing Voice and Nonvoice Sound Recognitions for Electric Equipment Control
|
Tsai, Wen-Chung; Shih, You-Jyun; Huang, Nien-Ting |
| 臺大學術典藏 |
2020-12-16T03:02:45Z |
Hardware-Assisted MMU Redirection for In-Guest Monitoring and API Profiling
|
Hsiao, S.-W.;Sun, Y.S.;Chen, M.C.; Hsiao, S.-W.; Sun, Y.S.; Chen, M.C.; YEALI SUN |
| 國立交通大學 |
2014-12-08T15:23:22Z |
Hardware-assisted Syntax Decoding Model for Software AVC/H.264 Decoders
|
Wu, Ming-Ju; Chen, Yi-Tseng; Tsai, Chun-Jen |
| 國立交通大學 |
2019-04-02T06:00:27Z |
Hardware-Based Courseware for Teaching the Theory of Transmission Lines
|
Tsai, Zuo-Min; Wang, Yu-Syuan |
| 國立成功大學 |
2023-09 |
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching
|
Chang;Cheng-Tsung;Chen;Pin-Wei;Chin;Wen-Long;Chou;Shih-Hsiang;Yang;Yu-Hua |
| 國立臺灣大學 |
2003 |
Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder
|
Lian, Chung-Jr; Yang, Zhong-Lan; Chang, Hao-Chieh; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:45Z |
Hardware-efficient architecture design for zerotree coding in MPEG-4 still texture coder
|
Lian, C.-J.; Yang, Z.-L.; Chang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T03:43:43Z |
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding
|
Chang, Hao-Chieh; Yang, Zhong-Lan; Lian, Chung-Jr; Chen, Liang-Gee; LIANG-GEE CHEN |
| 國立臺灣大學 |
2001-05 |
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding
|
Chang, Hao-Chieh; Yang, Zhong-Lan; Lian, Chung-Jr; Chen, Liang-Gee |
| 臺大學術典藏 |
2005-06 |
Hardware-efficient architecture design of wavelet-based adaptive visible watermarking
|
Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai; Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai |
| 國立臺灣大學 |
2005-06 |
Hardware-efficient architecture design of wavelet-based adaptive visible watermarking
|
Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai |
| 臺大學術典藏 |
2018-09-10T07:26:41Z |
Hardware-efficient belief propagation
|
Liang, C.-K.;Cheng, C.-C.;Lai, Y.-C.;Chen, L.-G.;Chen, H.H.; Liang, C.-K.; Cheng, C.-C.; Lai, Y.-C.; Chen, L.-G.; Chen, H.H.; LIANG-GEE CHEN; HOMER H. CHEN |
| 臺大學術典藏 |
2018-09-10T08:34:18Z |
Hardware-efficient belief propagation
|
HOMER H. CHEN; LIANG-GEE CHEN; Chen, H.H.; Chen, L.-G.; Liang, C.-K.;Cheng, C.-C.;Lai, Y.-C.;Chen, L.-G.;Chen, H.H.; Liang, C.-K.; Cheng, C.-C.; Lai, Y.-C. |
| 國立交通大學 |
2014-12-08T15:44:50Z |
Hardware-efficient DFT designs with cyclic convolution and subexpression sharing
|
Chang, TS; Guo, JI; Jen, CW |
| 國立交通大學 |
2014-12-08T15:30:54Z |
Hardware-Efficient EVD Processor Architecture in FastICA for Epileptic Seizure Detection
|
Shih, Yi-Hsin; Chen, Tsan-Jieh; Yang, Chia-Hsiang; Chiueh, Herming |
| 臺大學術典藏 |
2018-09-10T09:22:19Z |
Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection
|
Shih, Y.-H.; Chen, T.-J.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG |
| 國立成功大學 |
2012-05 |
Hardware-Efficient Filterbank Design for Fast Recursive MDST and IMDST Algorithms
|
Lai, Shin-Chi; Yeh, Yi-Ping; Lei, heau-Fang |
| 國立交通大學 |
2014-12-08T15:46:06Z |
Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs
|
Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:43:18Z |
Hardware-efficient pipelined programmable FIR filter design
|
Chang, TS; Jen, CW |
| 臺大學術典藏 |
2018-09-10T09:22:24Z |
Hardware-efficient true motion estimator based on Markov Random Field motion vector correction
|
Chen, F.-C.; Huang, Y.-L.; Chien, S.-Y.; SHAO-YI CHIEN |
| 臺大學術典藏 |
2020-06-16T06:38:10Z |
Hardware-Efficient Two-Stage Saliency Detection
|
Wu, S.-Y.;Lin, Y.-S.;Tu, W.-C.;Chien, S.-Y.; Wu, S.-Y.; Lin, Y.-S.; Tu, W.-C.; Chien, S.-Y.; SHAO-YI CHIEN |
| 國立臺灣大學 |
2008 |
Hardware-Enhanced Association Rule Mining with Hashing and Pipeling
|
Wen, I.-S.; Huang, J.-W.; Chen, M.-S. |
| 臺大學術典藏 |
2018-09-10T07:02:38Z |
Hardware-enhanced association rule mining with hashing and pipelining
|
Wen, Y.-H.; Huang, J.-W.; Chen, M.-S.; MING-SYAN CHEN |
| 大葉大學 |
2009 |
Hardware-in-the-Loop Experiments of Vehicle Stability Control for a Brake-by-Wire System
|
Chen, Chih-Keng;Dao, Trung-Kien |
| 大葉大學 |
2008 |
Hardware-in-the-Loop Experiments of Vehicle Stability Control for a Brake-by-Wire System
|
Chen, Chih-Keng;Dao, Trung-Kien |
| 大葉大學 |
2009 |
Hardware-in-the-Loop Experiments of Vehicle Stability Control system via a hydraulic model
|
Chen, Chih-Keng;Dao, Trung-Kien;Hsieh, Sen-Hsiung |
| 大葉大學 |
2009 |
Hardware-in-the-Loop Experiments of Vehicle Stability Control via a Hydraulic Model
|
Chen, Chih-Keng;Dao, Trung-Kien;Hsieh, Sen-Hsiung |
| 臺大學術典藏 |
2021-10-21T23:27:22Z |
Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control
|
Chung, Yi; YEE-PIEN YANG |
| 臺大學術典藏 |
2022-03-22T08:26:06Z |
Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control
|
Chung Y;Yang Y.-P.; Chung Y; Yang Y.-P.; YEE-PIEN YANG |
| 臺大學術典藏 |
2022-03-22T08:28:55Z |
Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control
|
Chung Y;Yang Y.-P.; Chung Y; Yang Y.-P.; YEE-PIEN YANG |
| 臺大學術典藏 |
2022-03-22T08:28:55Z |
Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control
|
Chung Y;Yang Y.-P.; Chung Y; Yang Y.-P.; YEE-PIEN YANG |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Hardware-oriented design for weighted median filters
|
Chen, Chun-Te;Chen, Liang-Gee;Hsiao, Jue-Hsuan; Chen, Chun-Te; Chen, Liang-Gee; Hsiao, Jue-Hsuan; LIANG-GEE CHEN |
| 國立臺灣大學 |
2008 |
Hardware-oriented image inpainting for perceptual I-frame error concealment
|
Chen, Ching-Yi; Wu, Guan-Lin; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T07:03:43Z |
Hardware-oriented image inpainting for perceptual I-frame error concealment
|
Chen, Ching-Yi; Wu, Guan-Lin; Chien, Shao-Yi; SHAO-YI CHIEN; Chen, Ching-Yi |
| 國立交通大學 |
2019-10-05T00:09:44Z |
HARDWARE-ORIENTED MEMORY-LIMITED ONLINE FASTICA ALGORITHM AND HARDWARE ARCHITECTURE FOR SIGNAL SEPARATION
|
Van, Lan-Da; Lu, Tsung-Che; Jung, Tzyy-Ping; Wang, Jo-Fu |
| 臺大學術典藏 |
2003-05 |
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder
|
Hsu, Chih-Wei; Chang, Yung-Chi; Chao, Wei-Min; Chen, Liang-Gee; Hsu, Chih-Wei; Chang, Yung-Chi; Chao, Wei-Min; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-05 |
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder
|
Hsu, Chih-Wei; Chang, Yung-Chi; Chao, Wei-Min; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:45Z |
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder
|
Hsu, C.-W.; Chang, Y.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立成功大學 |
2012-12 |
Hardware-software co-design architecture for Joint Photo Expert Graphic XR encoder
|
Tseng, C. -F.; Lai, Y. -T. |
| 國立臺灣科技大學 |
2009 |
Hardware-software codesign for high-speed signature-based virus scanning
|
Lin Y.-D.; Lin P.-C.; Lai Y.-C.; Liu T.-Y. |
