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Institution	Date	Title	Author
國立交通大學	2014-12-08T15:26:21Z	Layout design of high-quality SOI varactor	Chen, HY; Chen, KM; Huang, GW; Huang, CH; Yang, TH; Chang, CY
國立交通大學	2014-12-08T15:26:43Z	Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process	Ker, MD; Chuang, CH; Lo, WY
國立交通大學	2014-12-08T15:43:05Z	Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit	Ker, MD; Chen, TY
國立臺灣科技大學	2003	Layout Improvement for the Facility Design of Semiconductor Fabrication	Chen, J. C. ; Peng, G. M. ; Sun, C. J. ; Wang, J. J. ; Chang, P. F. ; Dai, R. D.
中原大學	2003-03	Layout Improvement for the Facility Design of Semiconductor Fabrication	J. C. Chen;G. M. Peng;C. J. Sun;J. J. Wang;P. F. Chang;R. D. Dai;
國立臺灣科技大學	2004	Layout Improvement for Wafer Fabrication Plants	Chen, J. C. ; Yang, R. T. ; Peng, K. M. ; Wang, C. C.
中原大學	2004-03	Layout Improvement for Wafer Fabrication Plants	J. C. Chen;R. T. Yang;K. M. Peng;C. C. Wang;
臺大學術典藏	2022-09-21T23:30:15Z	Layout of 1.50-inch, 3207-ppi oled display with oslsi/silsi structure capable of division driving fabricated through vlsi process with side-by-side patterning by photolithography	Saito, Toshihiko; Mizuguchi, Toshiki; Okamoto, Yuki; Ito, Minato; Toyotaka, Kouhei; Kozuma, Munehiro; Matsuzaki, Takanori; Kobayashi, Hidetomo; Onuki, Tatsuya; Hiura, Yoshikazu; Hodo, Ryota; Sasagawa, Shinya; Kunitake, Hitoshi; Nakamura, Daiki; Sato, Hitomi; Kimura, Hajime; Wu, Chih Chiang; Yoshida, Hiroshi; Chen, Min Cheng; MING-HAN LIAO; Chang, Shou Zen; Yamazaki, Shunpei
國立交通大學	2017-04-21T06:49:53Z	Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits	Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou
國立交通大學	2014-12-08T15:25:51Z	Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces	Chang, WJ; Ker, MD

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