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Institution	Date	Title	Author
國立臺灣大學	1986-09	Layout System Vol. 4:an Automatic Placement System for VLSI Layouts	Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立交通大學	2014-12-08T15:25:40Z	Layout techniques for on-chip interconnect inductance reduction	Tu, SW; Jou, JY; Chang, YW
臺大學術典藏	2018-09-10T04:53:44Z	Layout techniques for on-chip interconnect inductance reduction	Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG
義守大學	2011	Layout 設計與電磁相容之研究	陳安吉; An-Chi chen
國立中山大學	2006-08	Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis	X.L. Li;S.J. Wang;K.S.M. Li
國立中山大學	2006-08	Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage	K.L. Peng;S.J. Wang;K.S.M. Li
國立交通大學	2019-10-05T00:09:48Z	Layout-Based Dual-Cell-Aware Tests	Wu, Tse-Wei; Lee, Dong-Zhen; Wu, Kai-Chiang; Huang, Yu-Hao; Chen, Ying-Yen; Chen, Po-Lin; Chern, Mason; Lee, Jih-Nung; Kao, Shu-Yi; Chao, Mango C. -T.
國立交通大學	2017-04-21T06:56:48Z	Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level	Huang, Hsuan-Ming; Wen, Charles H. -P.
臺大學術典藏	2018-09-10T15:33:11Z	Layout-Dependent Effects-Aware Analytical Analog Placement	Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG
國立交通大學	2014-12-08T15:27:35Z	Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs	Yeh, Kuo-Liang; Guo, Jyh-Chyurn

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