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Institution	Date	Title	Author
臺大學術典藏	2019-10-24T07:57:26Z	Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine	吳安宇;AN-YEU(ANDY) WU;An-Yeu (Andy) Wu;Ding-Yuan Lee;Ting-Sheng Chen;Chia-Heng Wu; Chia-Heng Wu; Ting-Sheng Chen; Ding-Yuan Lee; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU; 吳安宇
臺大學術典藏	2020-06-11T06:34:18Z	Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine	Wu, C.-H.;Chen, T.-S.;Lee, D.-Y.;Liu, T.-T.;Wu, A.-Y.; Wu, C.-H.; Chen, T.-S.; Lee, D.-Y.; Liu, T.-T.; Wu, A.-Y.; TSUNG-TE LIU
國立成功大學	2005-04-23	Low-latitude ELF-whistlers observed in Taiwan	Wang, Yun-Ching; Wang, Kaiti; Su, Han-Tzong; Hsu, Rue-Ron
國立中山大學	2000	low-latitude ionospheric effects during a moderate storm by tomographic imaging	J.S. Xu;S.Y. Ma;X.B. Wu;K.H. Lin;K.C. Yeh
國立成功大學	2014-06	Low-latitude midnight brightness in 630.0 nm limb observations by FORMOSAT-2/ISUAL	Rajesh, P. K.; Chen, C. H.; Lin, C. H.; Liu, J. Y.; Huba, J. D.; Chen, A. B.; Hsu, R. R.; Chen, Y. T.
國立暨南國際大學	2003	Low-leakage 0.11 mu m CMOS for low-power RF-ICs and SRAMs applications?	林佑昇; Lin, YS
國立彰化師範大學	2008-12	Low-Leakage and Low-Power Implementation of High-Speed 65nm Logic Gates	Wu, Tsung-Yi; Lu, Liang-Ying; Liang, Cheng-Hsun
國立成功大學	2009-04	Low-Leakage and Low-Power Implementation of High-Speed Logic Gates	Wu, Tsung-Yi; Lu, Liang-Ying
國立彰化師範大學	2009	Low-Leakage and Low-Power Implementation of High-Speed Logic Gates	Wu, Tsung-Yi ; Lu, Liang-Ying
國立交通大學	2017-04-21T06:55:58Z	Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process	Lin, Chun-Yu; Wu, Yi-Han; Ker, Ming-Dou

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