| 中華大學 |
2009 |
Low-Power Multiplier Design with Row and Column Bypassing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters
|
謝曜式; Shieh, Yaw-Shih |
| 國立交通大學 |
2014-12-08T15:35:28Z |
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
|
Wang, Dao-Ping; Lin, Hon-Jarn; Chuang, Ching-Te; Hwang, Wei |
| 國立臺灣大學 |
1998 |
Low-Power Multirate Architecture for IF Digital Frequency Down-Converter
|
Shyh-Jye Jou; Shou-Yang Wu; 汪重光; Shyh-Jye Jou; Shou-Yang Wu; Wang, Chorng-Kuang |
| 臺大學術典藏 |
2004-05 |
Low-power parallel tree architecture for full search block-matching motion estimation
|
Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee; Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Low-power parallel tree architecture for full search block-matching motion estimation
|
Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
Low-power parallel tree architecture for full search block-matching motion estimation
|
Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立成功大學 |
2022-04 |
Low-Power Photodetectors Based on PVA-Modified Reduced Graphene Oxide Hybrid Solutions
|
Shih;Yi-Shan;Li;Wei-Chen;Shen;Jun-Hao;Chu;Shao-Yu;Uen;Wu-Yih;Lee;Hsin-Ying;Lin;Gong-Ru;Chen;Yu-Cheng;Tu;Wei-Chen |
| 國立臺灣科技大學 |
2019 |
Low-power photovoltaic energy harvesting with parallel differential power processing using a SEPIC
|
Bagci, F.S.;Liu, Y.-C.;Kim, Kim K.A. |
| 國立交通大學 |
2014-12-08T15:11:13Z |
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
|
Chen, Wei-Zen; Huang, Guan-Sheng |
| 朝陽科技大學 |
2014-01-01 |
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
|
林進發 |
| 朝陽科技大學 |
2012-02 |
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse -Enhancement Scheme
|
黃穎聰,林進發, 許明華 |
| 國立臺灣科技大學 |
2012 |
Low-power quadrature voltage-controlled oscillator formed with two injection-locked frequency dividers
|
Jang, S.-L.;Chou, L.-T. |
| 臺大學術典藏 |
2018-09-10T06:03:20Z |
Low-Power Radio Design for Wireless Smart Sensor Networks
|
W.-C. Fang; T.-H. Lin; TSUNG-HSIEN LIN |
| 國立成功大學 |
2009-04 |
Low-power register-exchange survivor memory architectures for Viterbi decoders
|
Shieh, Ming-Der; Wang, T. P.; Yang, D. W. |
| 臺大學術典藏 |
2018-09-10T15:33:17Z |
Low-power resistive random access memory by confining the formation of conducting filaments
|
Huang, Y.-J.; Shen, T.-H.; Lee, L.-H.; Wen, C.-Y.; Lee, S.-C.; Huang, Y.-J.; Shen, T.-H.; Lee, L.-H.; Wen, C.-Y.; Lee, S.-C.; SI-CHEN LEE |
| 國立臺灣科技大學 |
2011 |
LOW-POWER SELF-INJECTION-LOCKED CMOS ARMSTRONG VOLTAGE-CONTROLLED OSCILLATOR
|
Jang, S.L.;Liao, Y.H.;Chang, C.W.;Juang, M.H. |
| 國立中山大學 |
2005 |
Low-power small-area digital I/O cell
|
C.C. Wang;C.L. Lee;Y.L. Tseng;C.S. Chen;R. Hu |
| 國立中山大學 |
2005-12 |
Low-power small-area digital I/O cell
|
C.C. Wang;C.L. Lee;Y.L. Tseng;C.S. Chen;R. Hu |
| 國立中山大學 |
1995-08 |
Low-power state assignment by greedy state pair grouping
|
C.C. W;Y.L. Fan |
| 國立交通大學 |
2014-12-08T15:22:52Z |
Low-Power Sub-Harmonic Direct-Conversion Receiver With Tunable RF LNA and Wideband LO Generator at U-NII Bands
|
Syu, Jin-Siang; Meng, Chinchun |
| 淡江大學 |
2004-06 |
Low-power switched-capacitor filters for telecommunication applications
|
簡丞志; Chien, Cheng-chih; Chiang, Jen-shiun; Tu, Ming-hung; Sung, Yu-cheng; Lee, Yi-tsung |
| 國立臺灣科技大學 |
2017 |
Low-power three-path inductor class-C VCO without any dynamic bias circuit
|
Jang, S.-L.;Lin, Y.-C. |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
Low-power traceback MAP decoding for double-binary convolutional turbo decoder
|
Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
