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Taiwan Academic Institutional Repository >
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Showing items 90601-90610 of 2348487 (234849 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T09:50:56Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
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Liu, T.-T.;Rabaey, J.M.; Liu, T.-T.; Rabaey, J.M.; TSUNG-TE LIU |
| 臺大學術典藏 |
2019-10-31T07:12:33Z |
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
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HSIN-SHU CHEN;Wen-Jong Wu;Micka?l Lallart;Hsin-Shu Chen;Kai-Ren Cheng; Kai-Ren Cheng; Hsin-Shu Chen; Micka?l Lallart; Wen-Jong Wu; HSIN-SHU CHEN |
| 臺大學術典藏 |
2020-01-17T07:48:26Z |
A 0.25�gm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
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WEN-JONG WU;Wu, W.-J.;Lallart, M.;Chen, H.-S.;Cheng, K.-R.; Cheng, K.-R.; Chen, H.-S.; Lallart, M.; Wu, W.-J.; WEN-JONG WU |
| 國立臺灣科技大學 |
2010-03 |
A 0.3 V Cross-Coupled VCO Using Dynamic Threshold MOSFET
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Sheng-Lyang Jang;Chuang-Jen Huang;Ching-Wen Hsue;Chia-Wei Chang |
| 朝陽科技大學 |
2021-10-02 |
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications
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Lin,Jin-Fa; Tsai, Chang-Ming; Tsai, Ming-Yan; Hsia, Shih-Chang; Morsalin, S. M. Salahuddin; Sheu, Ming-Hwa; 林進發 |
| 國立臺灣大學 |
2004 |
A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-μm CMOS technology
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Tsai, Ming-Da; Wang, Huei |
| 臺大學術典藏 |
2020-06-11T06:16:48Z |
A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator
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Chang, C.-K.;Tsai, Y.-K.;Cheng, K.-H.;Lu, L.-H.; Chang, C.-K.; Tsai, Y.-K.; Cheng, K.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 國立交通大學 |
2015-07-21T08:29:40Z |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
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Lu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin |
| 臺大學術典藏 |
2020-06-11T06:31:42Z |
A 0.33 V 683 μW K-band transformer-based receiver front-end in 65 nm CMOS technology
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Cheng, J.-H.;Hsieh, C.-L.;Wu, M.-H.;Tsai, J.-H.;Huang, T.-W.; Cheng, J.-H.; Hsieh, C.-L.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
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Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
Showing items 90601-90610 of 2348487 (234849 Page(s) Totally)
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