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Institution	Date	Title	Author
國立中山大學	2000-02	A 1.0 GHz 0.6-µm 8-bit carry lookahead adder using PLA-styled all-N-transistor logic	C.C. Wang;C.J. Huang;K.C. Tsai
國立中山大學	1997-08	A 1.0 GHz 64-bit parallel comparator using two-phase clocking ANT dynamic logic	C.C. Wang;K.C. Tsai
國立中山大學	2001-09	A 1.0 GHz clock generator design with a negative delay using a single-shot locking method	C.C. Wang;Y.L. Tseng;R.S. Kao
臺大學術典藏	2018-09-10T09:16:57Z	A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition	LIANG-GEE CHEN; Chen, L.-G.; Tsai, C.-Y.; Lee, Y.-J.; Chen, C.-T.
國立成功大學	2023	A 1.0�fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process	Wang, C.-C.;Sangalang, R.G.B.;Tseng, I.-T.;Chiu, Y.-J.;Lin, Y.-C.;Jose, O.L.J.A.
國立交通大學	2020-10-05T02:02:22Z	A 1.1-3.1-GHz Tunable Quadruplexer with Compact Size and Bandwidth Control	Chi, Pei-Ling; Chi, Yu-Wen; Yang, Tao
臺大學術典藏	2020-04-28T07:12:59Z	A 1.1-V CMOS frequency synthesizer with pass-transistor-logic prescaler for U-NII band system	Cheng, J.-L.; Wang, C.-S.; Li, W.-C.; Wang, C.-K.; WEI-CHANG LI
國立交通大學	2019-12-13T01:12:52Z	A 1.16-3.89-GHz Tunable Six-Channel Diplexer with Compact Size and High Isolation	Chi, Pei-Ling; Chiou, Ching-Kai
臺大學術典藏	2022-02-14T23:56:07Z	A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices	Yu, Sheng Jung; Lee, Yu Chi; CHIA-HSIANG YANG
國立臺灣大學	2004	A 1.1G MAC/s Sub-Word-Parallel Digital Signal Processor for Wireless Communication Applications	Huang, Yuan-Hao; Ma, Hsi-Pin; Liou, Ming-Luen; Chiueh, Tzi-Dar

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