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Showing items 90816-90825 of 2348487 (234849 Page(s) Totally) << < 9077 9078 9079 9080 9081 9082 9083 9084 9085 9086 > >> View [10|25|50] records per page
| 國立中山大學 |
2000-12 |
A 1.25 GHz 8-bit tree-structured carry lookahead adder
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C.C. Wang;P.M. Lee;C.J. Huang;R.C. Lee |
| 國立臺灣科技大學 |
2008 |
A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition
|
Oulee C.-S.; Yang R.-J. |
| 臺大學術典藏 |
2018-09-10T08:18:16Z |
A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression
|
Chao-Ching Hung;I-Fong Chen;Shen-Iuan Liu; Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立中山大學 |
2003-08 |
A 1.26ns access time current-mode sense amplifier design for SRAMs
|
C.C. Wang;Y.L. Tseng;C.C. Li;R. Hu |
| 元智大學 |
2015-08-04 |
A 1.2V 3.5Gbps Digitalized LVDS driver in 0.18um CMOS technology
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Jhih-Siang Shao; Shi-Fung Zhou; Hungwen Lin |
| 淡江大學 |
1997-08 |
A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
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Cheng, Kuo-Hsing; Yee, Liow Yu; Liaw, Yii-Yih; Yang, Wei-Bin |
| 淡江大學 |
1997-08-21 |
A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process
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鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Laiw, Yii-yih |
| 臺大學術典藏 |
2020-06-11T06:45:52Z |
A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique
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Wang, Y.-S.;Hsieh, M.-H.;Liu, C.-M.;Wu, Y.-C.;Lin, B.-F.;Chiu, H.-C.;Chen, C.C.-P.; Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Wu, Y.-C.; Lin, B.-F.; Chiu, H.-C.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 國立臺灣大學 |
2005-02 |
A 1.2V 6.7mW impulse-radio UWB baseband transceiver
|
Yang, Chia-Hsiang; Chen, Kuan-Hung; Chiueh, Tzi-Dar |
| 臺大學術典藏 |
2018-09-10T05:23:20Z |
A 1.2V 6.7mW impulse-radio UWB baseband transceiver
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Yang, C.-H.; Chen, K.-H.; Chiueh, T.-D.; CHIA-HSIANG YANG |
Showing items 90816-90825 of 2348487 (234849 Page(s) Totally) << < 9077 9078 9079 9080 9081 9082 9083 9084 9085 9086 > >> View [10|25|50] records per page
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