| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system
|
Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 國立中山大學 |
2005-11 |
A 19-T full adder with high impedance circuits and conflict circuits for mobile devices’ controllers
|
C.C. Wang;Y.L. Tseng;Y.S. Chang |
| 國立交通大學 |
2019-12-13T01:12:53Z |
A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS
|
Sun, Wei-Che; Kuo, Chien-Nan |
| 臺大學術典藏 |
2021-12-21T23:17:04Z |
A 19.7-38.9-GHz Ultrabroadband PA With Phase Linearization for 5G in 28-nm CMOS Process
|
TIAN-WEI HUANG; Yen, Ho Ching; Tsai, Jeng Han; Bai, Wei Ting; Hung, Jui Cheng; Liang, You Jen |
| 臺大學術典藏 |
2018-09-10T14:57:24Z |
A 190-GHz amplifier with gain-boosting technique in 65-nm CMOS
|
Siao, D.-S.;Kao, J.-C.;Hsiao, Y.-H.;Hsu, Y.-W.;Teng, Y.-M.;Huang, G.-W.;Lin, K.-Y.;Wang, H.; Siao, D.-S.; Kao, J.-C.; Hsiao, Y.-H.; Hsu, Y.-W.; Teng, Y.-M.; Huang, G.-W.; Lin, K.-Y.; Wang, H.; KUN-YOU LIN |
| 臺大學術典藏 |
2020-06-04T07:54:10Z |
A 190-GHz amplifier with gain-boosting technique in 65-nm CMOS
|
Siao, D.-S.;Kao, J.-C.;Hsiao, Y.-H.;Hsu, Y.-W.;Teng, Y.-M.;Huang, G.-W.;Lin, K.-Y.;Wang, H.; Siao, D.-S.; Kao, J.-C.; Hsiao, Y.-H.; Hsu, Y.-W.; Teng, Y.-M.; Huang, G.-W.; Lin, K.-Y.; Wang, H.; HUEI WANG |
| 臺大學術典藏 |
2018-09-10T09:48:03Z |
A 191μW BPSK demodulator for data and power telemetry in biomedical implants
|
Wang, L.-L.;Yang, C.-H.;Chiueh, H.; Wang, L.-L.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2018-09-10T15:18:27Z |
A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications
|
Chen, L.-G.; LIANG-GEE CHEN; Chen, H.-H.;Huang, C.-T.;Wu, S.-S.;Hung, C.-L.;Ma, T.-C.;Chen, L.-G.; Chen, H.-H.; Huang, C.-T.; Wu, S.-S.; Hung, C.-L.; Ma, T.-C. |
| 臺大學術典藏 |
2018-09-10T08:18:17Z |
A 198.9GHz ~201.0GHz injection-locked frequency divider in 65nm CMOS
|
Bo-Yu Lin;I-Ting Lee;Chiao-Hsing Wang;Shen-Iuan Liu; Bo-Yu Lin; I-Ting Lee; Chiao-Hsing Wang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2018-09-10T15:20:07Z |
A 1D Electrospun Nanofiber Channel for Organic Field-Effect Transistors Using a Donor/Acceptor Planar Heterojunction Architecture
|
WEN-CHANG CHEN; Chen, W.-C.; Liu, C.-L.; Shih, C.-C.; Chang, H.-C. |
| 臺大學術典藏 |
2020-01-14T03:34:04Z |
A 1D–2D coupled SPH-SWE model applied to open channel flow simulations in complicated geometries
|
Chang K.-H.;Sheu T.W.-H.;Chang T.-J.; Chang K.-H.; Sheu T.W.-H.; Chang T.-J.; TSANG-JUNG CHANG |
| 臺大學術典藏 |
2020-01-17T07:47:28Z |
A 1D�V2D coupled SPH-SWE model applied to open channel flow simulations in complicated geometries
|
TONY W. H. SHEU; Chang, T.-J.; Chang, K.-H.; Sheu, T.W.-H. |
| 國立臺灣大學 |
2004-05 |
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors
|
Wu, Chia-Hsin; Liao, Jieh-Wei; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T03:50:27Z |
A 1V 5.8GHz CMOS Low Noise Amplifier in a 0.35um CMOS Process
|
Chih-Chun Tang; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立臺灣大學 |
2002 |
A 1V 5.8GHz low noise amplifier in a 0.35um standard CMOS process
|
Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 1V 50 GHz Digital-Controlled CMOS Frequency Divider
|
Bai, Shuen-Yin; Luo, Tang-Nian; Chen, Yi-Jan Emery |
| 臺大學術典藏 |
2018-09-10T05:51:54Z |
A 1V 50 GHz digital-controlled CMOS frequency divider
|
Bai, S.-Y.; Luo, T.-N.; Chen, Y.-J.E.; YI-JAN EMERY CHEN |
| 淡江大學 |
2006-08 |
A 1V 82dB Multibit Delta-Sigma Modulator
|
Kuo, Chien-Hung; Chang, Kang-Shuo; Jian, Jing-Shan |
| 國立臺灣師範大學 |
2014-10-30T09:28:40Z |
A 1V 82dB Multibit Delta-Sigma Modulator
|
Chien-Hung Kuo; Kang-Shuo Chang; Jing-Shan Jian |
| 國立臺灣師範大學 |
2006-08-11 |
A 1V 82dB Multibit Delta-Sigma Modulator
|
Chien-Hung Kuo; Kang-Shuo Chang; Jing-Shan Jian |
| 國立臺灣師範大學 |
2014-10-30T09:28:40Z |
A 1V 82dB Multibit Delta-Sigma Modulator
|
Chien-Hung Kuo; Kang-Shuo Chang; Jing-Shan Jian |
| 國立交通大學 |
2014-12-08T15:10:07Z |
A 1v CMOS low-noise amplifier with inductive resonated for 3.1-10.6GHz UWB wireless receiver
|
Huang, Zhe-Yang; Huang, Che-Cheng; Chen, Chun-Chieh; Hung, Chung-Chih |
| 國立臺灣大學 |
2008 |
A 1V CMOS Up-Converter for Dual-Band GPS/Galileo Receivers
|
Yu, Y.-H.; Hsu, W.-H.; Chen, Y.-J.E.; Kuo, C.F. |
| 臺大學術典藏 |
2018-09-10T06:56:16Z |
A 1V CMOS up-converter for dual-band GPS/Galileo receivers
|
Yu, Y.-H.; Hsu, W.-H.; Chen, Y.-J.E.; Kuo, C.F.; YI-JAN EMERY CHEN |
| 國立高雄師範大學 |
2007-12 |
A 1V Full-band Cascoded UWB LNA with Resistive Feedback
|
Ruey-Lue Wang;Min-Chuan Lin;Chih-Cheng Lin;Cheng-Fu Yang; 王瑞祿 |
| 國立聯合大學 |
2008 |
A 1V power supply operation CMOS subbandgap reference using switched capacitors
|
Chen, Hung-Wei; Luo, Jing-Yu; Yen, Wen-Cheng |
| 國立臺灣大學 |
2007 |
A 1V Wide Tuning Range VCO for UHF DTV Tuner
|
Yu, Yueh-Hua; Su, Feng-Kuan; Chen, Yi-Jan Emery; Heo, Deukhyoun |
| 淡江大學 |
2003-08 |
A 1V, 11-Bits Double-Sampling Delta-Sigma Modulator
|
郭建宏; Kuo, Chien-hung; Kao, Tsung-kai; Liu, Shen-Iuan |
| 國立交通大學 |
2014-12-08T15:10:06Z |
A 1V-2.39MW capacitor-coupling resonated low noise amplifier for 3-5GHz ultra-wideband system
|
Huang, Zhe-Yang; Huang, Che-Cheng; Chen, Chun-Chieh; Hung, Chung-Chih |
| 國立臺灣大學 |
2007-01 |
A 1x2 optical fiber switch using a dual-thickness SOI process
|
Yang, Y.-J.; Kuo, W.-C.; Fan, K.-C.; Lin, W.-L. |
| 臺大學術典藏 |
2021-11-25T04:06:58Z |
A 1x2 optical fiber switch using a dual-thickness SOI process
|
Y.-J. Yang; W.-C. Kuo; K.-C. Fan; W.-L. Lin; YAO-JOE YANG |
| 國立高雄第一科技大學 |
2005.01 |
A 1φ3W inverter with grid connection and active power filtering based on nonlinear programming and fast-zero-phase detection algorithm
|
Wu, Tsai-Fu;Shen, Chih-Lung;Nein, Hung-Shou;Li, Guang-Feng |
| 國立暨南國際大學 |
2011 |
A 2 76-mW, 3- TO 10-GHz ULTRAWIDEBAND LNA USING 0 18-mu m CMOS TECHNOLOGY
|
張錦法?; Chang, JF |
| 國立暨南國際大學 |
2011 |
A 2 76-mW, 3- TO 10-GHz ULTRAWIDEBAND LNA USING 0 18-mu m CMOS TECHNOLOGY
|
林佑昇?; Lin, YS |
| 國家衛生研究院 |
2003-08 |
A 2 center dot 6 Mb interval on chromosome 6q25.2-q25.3 is commonly deleted in human nasal natural killer/T-cell lymphoma
|
Sun, HS; Su, IJ; Lin, YC; Chen, JS; Fang, SY |
| 國立臺灣大學 |
2004-02 |
A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10GBase-LX4 Ethernet
|
Wu, Chia-Hsin; Liu, Chang-Shun; Liu, Shen-Iuan |
| 國立成功大學 |
2006-04 |
A 2 GHz, 0.25 mu m CMOS complementary VCO with differentially tuned MOS varactors for wireless applications
|
Lin, H. T.; Chu, Y. K.; Chuang, Huey-Ru |
| 國立交通大學 |
2015-07-21T08:31:31Z |
A 2 GOPS Quad-Mean Shift Processor with Early Termination for Machine Learning Applications
|
Tsai, Chang-Hung; Lee, Hui-Hsuan; Yu, Wan-Ju; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:09:17Z |
A 2 Ma record of explosive volcanism in southwestern Luzon: Implications for the timing of subducted slab steepening
|
Ku, Yueh-Ping; Chen, Chang-Hwa; Song, Sheng-Rong; Iizuka, Yoshiyuki; Shen, Jason Jiun-San |
| 臺大學術典藏 |
2018-09-10T07:32:29Z |
A 2 Ma record of explosive volcanism in southwestern Luzon: Implications for the timing of subducted slab steepening
|
Ku, Y.-P.;Chen, C.-H.;Song, S.-R.;Iizuka, Y.;Shen, J.J.-S.; Ku, Y.-P.; Chen, C.-H.; Song, S.-R.; Iizuka, Y.; Shen, J.J.-S.; SHENG-RONG SONG |
| 中原大學 |
2010-03-10 |
A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems
|
Alfonso Cesar B. Albason; Danny Wen-Yaw Chung; Shyh-Liang Lou |
| 中原大學 |
2010-03-10 |
A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems
|
Alfonso Cesar B. Albason; Danny Wen-Yaw Chung; Shyh-Liang Lou |
| 國立暨南國際大學 |
2009 |
A 2 mW, 55.8-GHz CMOS INJECTION-LOCKED FREQUENCY DIVIDER WITH 7.1-GHz LOCKING RANGE
|
陳世璋?; Chen, CZ |
| 國立暨南國際大學 |
2009 |
A 2 mW, 55.8-GHz CMOS INJECTION-LOCKED FREQUENCY DIVIDER WITH 7.1-GHz LOCKING RANGE
|
徐偉倫?; Hsu, WL |
| 國立暨南國際大學 |
2009 |
A 2 mW, 55.8-GHz CMOS INJECTION-LOCKED FREQUENCY DIVIDER WITH 7.1-GHz LOCKING RANGE
|
林佑昇?; Lin, YS |
| 臺大學術典藏 |
2000-08 |
A 2 V clock synchronizer using digital delay-locked loop
|
Hwang, Chorng-Sii; Chung, Wang-Chih; Wang, Chih-Yong; Tsao, Hen-Wai; Liu, Shen-Iuan; Hwang, Chorng-Sii; Chung, Wang-Chih; Wang, Chih-Yong; Tsao, Hen-Wai; Liu, Shen-Iuan |
| 國立臺灣大學 |
2000-08 |
A 2 V clock synchronizer using digital delay-locked loop
|
Hwang, Chorng-Sii; Chung, Wang-Chih; Wang, Chih-Yong; Tsao, Hen-Wai; Liu, Shen-Iuan |
| 國立臺灣大學 |
1999-08 |
A 2 V CMOS programmable pipelined digital differential matched filter for DS-CDMA system
|
Yen, She-Hwa; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2010 |
A 2 x 2 Split Cross-Bar Optical Switch Using a Hybrid Actuation Configuration
|
Liao, Bo-Ting; Chia, Bonnie Tingting; Shih, Sun-Chih; Fan, Kuang-Chao; Yang, Yao-Joe Joseph |
| 國立交通大學 |
2017-04-21T06:49:42Z |
A 2 x 20-Gb/s, 1.2-pJ/bit, Time-Interleaved Optical Receiver in 40-nm CMOS
|
Huang, Shih-Hao; Hung, Zheng-Hao; Chen, Wei-Zen |
