|
English
|
正體中文
|
简体中文
|
Total items :0
|
|
Visitors :
52530104
Online Users :
1365
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Title
|
Showing items 916766-916775 of 2348570 (234857 Page(s) Totally)
<< < 91672 91673 91674 91675 91676 91677 91678 91679 91680 91681 > >>
View [10|25|50] records per page
| 中國文化大學 |
2018-04 |
VLSI implementation of an ultra-low-cost and low-power image compressor for wireless camera networks
|
Chen, SL (Chen, Shih-Lun); Nie, J (Nie, Jing); Lin, TL (Lin, Ting-Lan); Chung, RL (Chung, Rih-Lung); Hsia, CH (Hsia, Chih-Hsien); Liu, TY (Liu, Tse-Yen); Lin, SY (Lin, Szu-Yin); Wu, HX (Wu, Hai-Xia) |
| 中華大學 |
2006 |
VLSI Implementation of CORDIC-Based Geometry Rotation for High-Speed 3-D Computer Graphic Systems
|
宋志雲; Sung, Tze-Yun |
| 國立中山大學 |
1997-06 |
VLSI Implementation of Digit-On-Line CORDIC with Constant Scaling Factor
|
Shen-Fu Hsiao; Jen-Yin Chen |
| 中華大學 |
2008 |
VLSI Implementation of Discrete Wavelet Transform with Lifting Scheme
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of Double- Rotation CORDIC Arithmetic
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
VLSI Implementation of Double- Rotation CORDIC Arithmetic (DRCA)
|
宋志雲; Sung, Tze-Yun |
| 國立中山大學 |
1994-12 |
VLSI Implementation of Fully Pipelined Hadamard Transform
|
Shen-Fu Hsiao; Vincent Tsai |
| 中華大學 |
2006 |
VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2007 |
VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems
|
宋志雲; Sung, Tze-Yun |
Showing items 916766-916775 of 2348570 (234857 Page(s) Totally)
<< < 91672 91673 91674 91675 91676 91677 91678 91679 91680 91681 > >>
View [10|25|50] records per page
|
