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Institution	Date	Title	Author
國立臺灣大學	2008	A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery	Liao, Chih-Fan; Liu, Shen-Iuan
臺大學術典藏	2018-09-10T07:08:34Z	A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery	Chih-Fan Liao;Shen-Iuan Liu; Chih-Fan Liao; Shen-Iuan Liu; SHEN-IUAN LIU
國立交通大學	2014-12-08T15:21:11Z	A 40-Gb/s OFDM PON System Based on 10-GHz EAM and 10-GHz Direct-Detection PIN	Chen, Hsing-Yu; Wei, Chia Chien; Hsu, Dar-Zu; Yuang, Maria C.; Chen, Jyehong; Lin, Yu-Min; Tien, Po-Lung; Lee, Steven S. W.; Lin, Shih-Hsuan; Li, Wei-Yuan; Hsu, Chih-Hung; Shih, Ju-Lin
臺大學術典藏	2018-09-10T08:46:27Z	A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm	Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU
國立臺灣大學	2004-04	A 40-GHz Frequency Divider in 0.18-m CMOS Technology	Lee, Jri; Razavi, Behzad
臺大學術典藏	2019-10-24T07:28:01Z	A 40-GHz high linearity transmitter in 65-nm CMOS technology with 32-dBm OIP3	王暉;HUEI WANG;Huei Wang;Chun-Nien Chen;Yen-Ting Lin;Tai-Yu Kuo; Tai-Yu Kuo; Yen-Ting Lin; Chun-Nien Chen; Huei Wang; HUEI WANG; 王暉
臺大學術典藏	2019-10-24T07:28:01Z	A 40-GHz high linearity transmitter in 65-nm CMOS technology with 32-dBm OIP3	王暉;HUEI WANG;Huei Wang;Chun-Nien Chen;Yen-Ting Lin;Tai-Yu Kuo; Tai-Yu Kuo; Yen-Ting Lin; Chun-Nien Chen; Huei Wang; HUEI WANG; 王暉
國立臺灣大學	2009	A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS	Hsieh, Hsieh-Hung; Lu, Liang-Hung
臺大學術典藏	2018-09-10T07:43:05Z	A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS	H.-H. Hsieh;L.-H. Lu; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU
臺大學術典藏	2009	A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS	Hsieh, H.-H.;Lu, L.-H.; Hsieh, H.-H.; Lu, L.-H.; LIANG-HUNG LU

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