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Showing items 92011-92020 of 2348823 (234883 Page(s) Totally) << < 9197 9198 9199 9200 9201 9202 9203 9204 9205 9206 > >> View [10|25|50] records per page
| 國立交通大學 |
2014-12-08T15:25:10Z |
A 40-nm-Gate InAs/In(0.7)Ga(0.3)As Composite-Channel HEMT with 2200 mS/mm and 500-GHz f(T)
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Kuo, Chien-I; Hsu, Heng-Tung; Wu, Chien-Ying; Chang, Edward Yi; Miyamoto, Yasuyuki; Chen, Yu-Lin; Biswas, Dhrubes |
| 元智大學 |
2009-05 |
A 40-nm-Gate InAs/InGaAs Composite-Channel HEMT with 2200 mS/mm and 500-GHz fT
|
許恒通; Chien-I Kuo; Chien-Ying Wu; Edward Yi Chang; Yasuyuki Miyamoto; Yu-Lin Chen; Dhrubes Biswas |
| 元智大學 |
2009-05 |
A 40-nm-Gate InAs/InGaAs Composite-Channel HEMT with 2200 mS/mm and 500-GHz fT
|
許恒通; Chien-I Kuo; Chien-Ying Wu; Edward Yi Chang; Yasuyuki Miyamoto; Yu-Lin Chen; Dhrubes Biswas |
| 臺大學術典藏 |
2020-06-11T06:16:47Z |
A 40.4-dB Range, 0.73-dB Step, and 0.07-dB Error Programmable Gain Amplifier Using Gain Error Shifting Technique
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Wang, L.-S.;Ku, P.-C.;Ko, P.-T.;Chung, C.-J.;Lu, L.-H.; Wang, L.-S.; Ku, P.-C.; Ko, P.-T.; Chung, C.-J.; Lu, L.-H.; LIANG-HUNG LU |
| 國立成功大學 |
2019 |
A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth
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Hung, T.-C.;Kuo, T.-H. |
| 淡江大學 |
2010-12-12 |
A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process
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施鴻源; 陳秋榜 |
| 淡江大學 |
2012-07-15 |
A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry
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Shih, Horng-Yuan; Chang, Yu-Chuan; Chen, Chun-Fan; Lin, Sheng-Kai |
| 臺大學術典藏 |
2018-09-10T08:19:11Z |
A 400-MHz Super-Regenerative Receiver with a Fast Digital Frequency Calibration
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H.-H. Liu;C.-J. Tung;Y.-H. Liu;T.-H. Lin; H.-H. Liu; C.-J. Tung; Y.-H. Liu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-μm CMOS
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K.-C. Liao;P.-S. Huang;W.-H. Chiu;T.-H. Lin; K.-C. Liao; P.-S. Huang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T09:42:58Z |
A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation
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Tsai, Y.-M.;Yang, T.-J.;Chen, L.-G.; Tsai, Y.-M.; Yang, T.-J.; Chen, L.-G.; LIANG-GEE CHEN |
Showing items 92011-92020 of 2348823 (234883 Page(s) Totally) << < 9197 9198 9199 9200 9201 9202 9203 9204 9205 9206 > >> View [10|25|50] records per page
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