|
English
|
正體中文
|
简体中文
|
总笔数 :0
|
|
造访人次 :
53338890
在线人数 :
649
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
显示项目 313256-313265 / 2348964 (共234897页)
<< < 31321 31322 31323 31324 31325 31326 31327 31328 31329 31330 > >>
每页显示[10|25|50]项目
| 中國文化大學 |
2004 |
Design of 1 × 3 MMI optical power dividers with rectangular waveguide cores based on silica substrate
|
Lee, Keh-Yi ; Tsai, Wei-Chih ; Chang, Fu-Chiang ; Lo, Kuo-Chang ; Lin, Yu-Jen |
| 臺大學術典藏 |
2020-06-11T06:23:57Z |
Design of 1-D and 2-D IIR Eigenfilters
|
Pei, S.-C.;Shyu, J.-J.; Pei, S.-C.; Shyu, J.-J.; SOO-CHANG PEI |
| 國立高雄第一科技大學 |
2002.10 |
Design of 1-D and 2-D variable fractional delay allpass filters using weighted least-squares method
|
Tseng, Chien-Cheng |
| 國立成功大學 |
2012 |
Design of 1-GSample/s 9-b BiCMOS track-and-hold amplifier with high linear input stage
|
Lin, Hung-Yi; Lai, Yen-Tai |
| 國立臺灣師範大學 |
2014-10-30T09:28:43Z |
Design of 1.2 V broadband, high data-rate CMOS MMW I/Q modulator and demodulator using modified Gilbert-cell mixer
|
Jeng-Han Tsai |
| 國立臺灣師範大學 |
2014-10-30T09:28:43Z |
Design of 1.2 V broadband, high data-rate CMOS MMW I/Q modulator and demodulator using modified Gilbert-cell mixer
|
Jeng-Han Tsai |
| 中原大學 |
2009-12 |
Design of 13-Bit Incremental Delta-Sigma ADC Using 0.35um CMOS Technology
|
Mark Anthony Te; Febus Reidj G. Cruz; Danny Wen-Yaw Chung; Roderick Yap |
| 國立交通大學 |
2018-08-21T05:57:04Z |
Design of 18 similar to 26GHz Receiver with Wideband RF, LO and IF in 0.15 mu m GaAs pHEMT Process
|
Chen, Ying; Yu, Zhong-I; Huang, Ching-Ying; Hsieh, Kuan-Han; Hu, Robert |
| 東海大學 |
1998-09-07 |
Design of 2 V 1 GHz CMOS low-noise bandpass amplifier with good temperature stability and low power dissipation
|
Wu, Chung-Yu, Gong, Jeng, Cheng, Yu |
| 國立交通大學 |
2014-12-08T15:32:16Z |
Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices
|
Ker, Ming-Dou; Chiu, Po-Yen |
显示项目 313256-313265 / 2348964 (共234897页)
<< < 31321 31322 31323 31324 31325 31326 31327 31328 31329 31330 > >>
每页显示[10|25|50]项目
|
