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显示项目 397556-397605 / 2348971 (共46980页)
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机构	日期	题名	作者
國立交通大學	2014-12-08T15:17:09Z	ESD failure mechanisms of analog I/O cells in 0.18-mu m CMOS technology	Ker, MD; Chen, SH; Chuang, CH
國立交通大學	2014-12-08T15:40:18Z	ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness	Ker, MD; Hsu, HC; Peng, JJ
國立交通大學	2014-12-08T15:19:14Z	ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology	Ker, MD; Chuang, CH; Lo, WY
國立交通大學	2014-12-08T15:26:45Z	ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration	Ker, MD; Chuang, CH
國立交通大學	2020-10-05T02:02:01Z	ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side	Chen, Hung-Wei; Chen, Shen-Li; Huang, Yu-Ting; Chen, Hsun-Hsiang
國立交通大學	2014-12-16T06:14:33Z	ESD protection circuit	Ker; Ming-Dou; Lin; Kun-Hsien
國立交通大學	2014-12-16T06:14:37Z	ESD protection circuit	Ker; Ming-Dou; Lin; Kun-Hsien
國立交通大學	2014-12-08T15:38:52Z	ESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchup	Ker, Ming-Dou; Hsu, Che-Lun; Chen, Wen-Yi
國立交通大學	2014-12-16T06:14:05Z	ESD protection circuitry with multi-finger SCRS	Ker Ming-Dou; Lin Chun-Yu; Wang Chang-Tzu
國立交通大學	2014-12-16T06:15:37Z	ESD PROTECTION CIRCUITRY WITH MULTI-FINGER SCRS	Ker, Ming-Dou; Lin, Chun-Yu; Wang, Chang-Tzu
國立交通大學	2014-12-08T15:26:38Z	ESD protection circuits with novel MOS-bounded diode structures	Ker, MD; Chuang, CH
國立交通大學	2014-12-08T15:18:29Z	ESD protection design for 1-to 10-GHz distributed amplifier in CMOS technology	Ker, MD; Hsiao, YW; Kuo, BJ
國立交通大學	2014-12-08T15:22:52Z	ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process	Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou
國立交通大學	2014-12-08T15:26:31Z	ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness	Ker, MD; Lo, WY; Lee, CM; Chen, CP; Kao, HS
國立交通大學	2014-12-08T15:26:31Z	ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness	Ker, MD; Lo, WY; Lee, CM; Chen, CP; Kao, HS
國立臺灣師範大學	2019-09-03T10:46:07Z	ESD Protection Design for Broadband Circuits	賴玉瑄; Lai, Yu-Hsuan
國立交通大學	2014-12-08T15:25:47Z	ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme	Ker, MD; Kuo, BJ
國立交通大學	2014-12-08T15:25:00Z	ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces	Chang, Wei-Jen; Ker, Ming-Dou
國立交通大學	2014-12-08T15:42:19Z	ESD protection design for CMOS RF integrated circuits using polysilicon diodes	Ker, MD; Chang, CY
國立交通大學	2014-12-08T15:46:07Z	ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR	Ker, Ming-Dou; Lin, Chun-Yu; Meng, Guo-Xuan
國立交通大學	2014-12-08T15:10:12Z	ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process	Hsiao, Yuan-Wen; Ker, Ming-Dou; Chiu, Po-Yen; Huang, Chun; Tseng, Yuh-Kuang
國立交通大學	2017-04-21T06:49:29Z	ESD Protection Design for Gigahertz Differential LNA in a 65-nm CMOS Process	Lin, Chun-Yu; Fan, Mei-Lian; Fu, Wei-Hao
國立交通大學	2018-08-21T05:56:49Z	ESD Protection Design for High-Speed Applications in CMOS Technology	Chen, Jie-Ting; Lin, Chun-Yu; Chang, Rong-Kun; Ker, Ming-Dou; Tzeng, Tzu-Chien; Lin, Tzu-Chiang
國立交通大學	2014-12-08T15:18:07Z	ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology	Ker, MD; Lin, KH
國立交通大學	2014-12-08T15:36:14Z	ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit	Ker, MD; Hsu, HC
國立交通大學	2014-12-08T15:26:34Z	ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process	Ker, MD; Chuang, CH; Hsu, KC; Lo, WY
國立交通大學	2014-12-08T15:25:20Z	ESD protection design for mixed-voltage I/O interfaces - Overview	Ker, Ming-Dou; Lin, Kun-Hsien
國立交通大學	2014-12-08T15:26:14Z	ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique	Ker, MD; Hsu, HC
國立交通大學	2015-07-21T08:31:29Z	ESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technology	Lin, Chun-Yu; Chu, Li-Wei; Tsai, Shiang-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Wei, Yu-Lin; Chang, Tzu-Heng
國立交通大學	2017-04-21T06:56:36Z	ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test	Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi
國立交通大學	2017-04-21T06:48:45Z	ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process	Chu, Li-Wei; Lin, Chun-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Tseng, Jen-Chou; Jou, Chewn-Pu; Tsai, Ming-Hsien
國立交通大學	2019-10-05T00:09:47Z	ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications	Hung, Tao-Yi; Ker, Ming-Dou
國立交通大學	2014-12-08T15:18:35Z	ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS	Ker, MD; Chang, WJ
國立交通大學	2014-12-08T15:44:57Z	ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications	Ker, MD; Chen, TY; Wu, CY; Chang, HH
國立交通大學	2018-08-21T05:57:09Z	ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process	Hung, Tao-Yi; Ker, Ming-Dou
國立交通大學	2014-12-08T15:38:36Z	ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins	Ker, MD; Chang, CY; Chang, YS
國立交通大學	2014-12-08T15:26:36Z	ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins	Ker, MD; Chang, CY; Chang, YS
國立交通大學	2019-08-02T02:18:28Z	ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains	Chen, Jie-Ting; Ker, Ming-Dou
國立交通大學	2017-04-21T06:49:12Z	ESD Protection Design with Latchup-Free Immunity in 120V SOI Process	Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih
國立交通大學	2014-12-08T15:38:25Z	ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology	Wang, Chang-Tzu; Ker, Ming-Dou
義守大學	2010-12	ESD Protection Design with Lateral DMOS Transistor in 40-V BCD Technology	Chang-Tzu Wang;Ming-Dou Ker
國立交通大學	2019-04-02T06:04:53Z	ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications	Ker, Ming-Don; Lin, Chun-Yu; Wu, Yi-Han; Wang, Wen-Tai
國立交通大學	2014-12-08T15:11:24Z	ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers	Ker, Ming-Dou; Chang, Wei-Jen
國立交通大學	2017-04-21T06:55:35Z	ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC	Dai, Chia-Tsen; Ker, Ming-Dou
國立交通大學	2017-04-21T06:50:10Z	ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC	Dai, Chia-Tsen; Ker, Ming-Dou
國立交通大學	2014-12-08T15:26:55Z	ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design	Chen, TY; Ker, MD
國立交通大學	2014-12-16T06:15:12Z	ESD PROTECTION STRUCTURE FOR 3D IC	Chen Kuan-Neng; Lai Ming-Fang; Chen Hung-Ming
國立交通大學	2014-12-08T15:25:32Z	ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications	Ker, MD; Chang, WJ; Yang, M; Chen, CC; Chan, MC; Shieh, WT; Yen, KL
國立交通大學	2014-12-08T15:28:05Z	ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process	Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Chang, Tzu-Heng
國立交通大學	2014-12-08T15:43:41Z	ESD protection under grounded-up bond pads in 0.13 mu m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology	Chou, KY; Chen, MJ

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