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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 634286-634295 / 2348964 (共234897页)
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每页显示[10|25|50]项目
| 國立臺灣科技大學 |
2014 |
On-chip miniaturized triplexer using lumped networks with dual resonators on an integrated passive device process
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Lai, C.-H.;Chung, W.-S.;Ma, T.-G. |
| 國立交通大學 |
2014-12-16T06:13:54Z |
On-chip noise filter circuit
|
Ker Ming-Dou; Yen Cheng-Cheng; Chen Tung-Yang |
| 國立交通大學 |
2014-12-16T06:15:06Z |
On-Chip Noise Filter Circuit
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Ker Ming-Dou; Yen Cheng-Cheng; Chen Tung-Yang |
| 臺大學術典藏 |
2022-01-15T00:08:40Z |
On-Chip Optical Routing with Provably Good Algorithms for Path Clustering and Assignment
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Lu, Yu Sheng; Yu, Sheng Jung; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-04-14T23:28:00Z |
On-chip Optical Routing with Waveguide Matching Constraints
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Chuang, Fu Yu; YAO-WEN CHANG |
| 國立交通大學 |
2020-10-05T02:01:07Z |
On-Chip Over-Voltage Protection Design Against Surge Events on the CC Pin of USB Type-C Interface
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Ke, Chao-Yang; Ker, Ming-Dou |
| 臺大學術典藏 |
2018-09-10T07:26:40Z |
On-chip principal component analysis with a mean pre-estimation method for spike sorting
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Chen, T.-C.;Chen, K.;Liu, W.;Chen, L.-G.; Chen, T.-C.; Chen, K.; Liu, W.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2006 |
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines
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Huang, Jiun-Lang |
| 臺大學術典藏 |
2018-09-10T06:03:13Z |
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines
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J.-L. Huang; JIUN-LANG HUANG |
| 國立成功大學 |
2018 |
On-chip real-time feature extraction using semantic annotations for object recognition
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Yu, Yu Y.-H.;Lee, T.-T.;Chen, P.-Y.;Kwok, N. |
显示项目 634286-634295 / 2348964 (共234897页)
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每页显示[10|25|50]项目
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