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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 262246-262255 / 2348973 (共234898頁)
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| 國立臺灣大學 |
2007 |
Clock Free Data Streams Alignment for Sensor Networks
|
Lee, Guo-Liang; Shih, Chi-Sheng |
| 臺大學術典藏 |
2007 |
Clock Free Data Streams Alignment for Sensor Networks.
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Lee, Guo-Liang; Shih, Chi-Sheng; CHI-SHENG SHIH |
| 元智大學 |
2011-03 |
Clock Gating Optimization with Delay-Matching
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Shih-Jung Hsu; Lin R.-B. |
| 臺大學術典藏 |
2018-09-10T06:37:56Z |
Clock generator having a 50% duty-cycle
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Tsung-Hsien Lin; TSUNG-HSIEN LIN |
| 中原大學 |
2002-08 |
Clock Period Minimization by Incorporating Clock Skew Scheduling and Gate-Level Delay Insertion
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Huang, Shih-Hsu;Nieh, Yow-Tyng |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Clock Planning for Multi-Voltage and Multi-Mode Designs
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Tsai, Chang-Cheng; Lin, Tzu-Hen; Tsai, Shin-Han; Chen, Hung-Ming |
| 國立中山大學 |
2004-12 |
Clock recovery and data recovery design for LVDS transceiver used in LCD panels
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C.C. Wang;C.L. Lee;C.Y. Hsiao;J.F. Huang |
| 國立中山大學 |
2004-06 |
Clock recovery and data recovery design for LVDS transceiver used in LCD panels
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C.C. Wang;C.L. Lee;C.Y. Hsiao;J.F. Huang |
| 臺大學術典藏 |
2018-09-10T09:25:33Z |
Clock Rescheduling for Timing Engineering Change Orders
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Kuan-Hsien Ho;Xin-Wei Shih;Jie-Hong R. Jiang; Kuan-Hsien Ho; Xin-Wei Shih; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 元智大學 |
2010-03 |
Clock Routing for Structured ASICs with Via-Configurable Fabrics
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林榮彬; I-Wei Lee; Wen-Hao Chen |
顯示項目 262246-262255 / 2348973 (共234898頁)
<< < 26220 26221 26222 26223 26224 26225 26226 26227 26228 26229 > >>
每頁顯示[10|25|50]項目
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