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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 295961-295970 / 2348881 (共234889頁)
<< < 29592 29593 29594 29595 29596 29597 29598 29599 29600 29601 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2005-06 |
Crosstalk- and Performance-Driven Multilevel Full-Chip Routing
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Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; Lee, Der-Tsai; Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; Lee, Der-Tsai |
| 國立臺灣大學 |
2005-06 |
Crosstalk- and Performance-Driven Multilevel Full-Chip Routing
|
Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; Lee, Der-Tsai |
| 國立臺灣大學 |
2005 |
Crosstalk- and performance-driven multilevel full-chip routing
|
Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; Lee, Der-Tsai |
| 國立臺灣大學 |
2005-06 |
Crosstalk- and Performance-Driven Multilevel Full-Chip Routing
|
Ho, T. Y.; Chang, Y. W.; Lee, S. J.; Chen, D.T. |
| 元智大學 |
2007-06 |
Crosstalk-aware domino-logic synthesis
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劉一宇; TingTing Hwang |
| 國立交通大學 |
2014-12-08T15:27:03Z |
Crosstalk-constrained performance optimization by using wire sizing and perturbation
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Pan, SR; Chang, YW |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
Crosstalk-constrained performance optimization by using wire sizing and perturbation
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Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG |
| 國立交通大學 |
2014-12-08T15:44:51Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
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Jiang, IHR; Chang, YW; Jou, JY |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG |
| 國立臺灣大學 |
2000 |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang |
顯示項目 295961-295970 / 2348881 (共234889頁)
<< < 29592 29593 29594 29595 29596 29597 29598 29599 29600 29601 > >>
每頁顯示[10|25|50]項目
|
