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顯示項目 461096-461105 / 2348570 (共234857頁) << < 46105 46106 46107 46108 46109 46110 46111 46112 46113 46114 > >> 每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2007-04-19T04:02:59Z |
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile
|
Chen, Liang-Gee;Chien, Shao-Yi;Huang, Yu-Wen;Chen, Ching-Yeh;Chao, Wei-Min; Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile
|
Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:19Z |
Hardware architecture for global motion estimation for MPEG-4 advanced simple profile
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Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立交通大學 |
2014-12-08T15:09:16Z |
Hardware Architecture for High-Performance Regular Expression Matching
|
Lee, Tsern-Huei |
| 中華大學 |
2011 |
Hardware Architecture of Real-Time Stereoscopic Image Generation from Depth Map
|
鄭芳炫; Cheng, Fang Hsuan |
| 國立臺灣大學 |
2007 |
Hardware Architecture to Realize Multi-layer Image Processing in Real-time
|
Fu, Li-Chen; Lu Chieh-Lun |
| 臺大學術典藏 |
2018-09-10T06:30:49Z |
Hardware architecture to realize multi-layer image processing in real-time
|
Fu, Li-Chen; Lu Chieh-Lun; LI-CHEN FU |
| 亞洲大學 |
2007-12-20 |
Hardware Context Switching Methodology for Dynamically Partially Reconfigurable Systems
|
Trong-Yen Lee; Che-Cheng Hu; Li-Wen Lai; Chia-Chun Tsai and Rong-Shue Hsiao |
| 國立成功大學 |
2016-06 |
Hardware Design and Implementation for Empirical Mode Decomposition
|
Chen, Pei-Yin; Lai, Yen-Chen; Zheng, Ju-Yang |
| 國立交通大學 |
2018-08-21T05:56:54Z |
Hardware Design for Statistical Network Traffic Classifiers
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Lu, Chun-Nan; Lai, Yuan-Cheng; Huang, Chun-Ying; Lin, Ying-Dar |
顯示項目 461096-461105 / 2348570 (共234857頁) << < 46105 46106 46107 46108 46109 46110 46111 46112 46113 46114 > >> 每頁顯示[10|25|50]項目
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