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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 461146-461155 / 2348511 (共234852頁)
<< < 46110 46111 46112 46113 46114 46115 46116 46117 46118 46119 > >>
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| 臺大學術典藏 |
2005-12 |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
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Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee; Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee |
| 國立臺灣大學 |
2005-12 |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
|
Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
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Chen, Y.-H.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2003-07 |
Hardware oriented rate control algorithm and implementation for realtime video coding
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Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee; Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-07 |
Hardware oriented rate control algorithm and implementation for realtime video coding
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Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware oriented rate control algorithm and implementation for realtime video coding
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Fang, H.-C.; Wang, T.-C.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立中山大學 |
1999-11 |
Hardware realization of a bit-serial 16-bit multiplier using low-power high-speed FPGA logic module for DSP applications
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C.C. Wang;C.J. Huang;H.L. Wu;H.M. Yang |
| 國立中山大學 |
1996-05 |
Hardware realization of multi-valued exponential bidirectional associative memory using current-mode circuits
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C.C. Wang;Y.C. Chen |
| 國立臺灣科技大學 |
2012 |
Hardware resource manager for reconfiguration system
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Lin, C.-T.;Horng, S.-J.;Huang, Y.-L. |
| 國立交通大學 |
2014-12-08T15:27:49Z |
HARDWARE SHARING IN TREE-STRUCTURE QMF BANKS
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LEE, HR; JEN, CW |
顯示項目 461146-461155 / 2348511 (共234852頁)
<< < 46110 46111 46112 46113 46114 46115 46116 46117 46118 46119 > >>
每頁顯示[10|25|50]項目
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